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PLL205-16

Part Number	PLL205-16
Manufacturer	PhaseLink
Description	Programmable Clock Generator
Published	Feb 9, 2006
Detailed Description	m Preliminary PLL205-16 o c . Programmable Clock Generator for VIA KT-266 Chipset U t4 FEATURES PIN CONFIGURATION e e fr...
Datasheet	PLL205-16 PDF File

Overview

m Preliminary PLL205-16 o c .
Programmable Clock Generator for VIA KT-266 Chipset U t4 FEATURES PIN CONFIGURATION e e frequencies for VIA KT266 • Generates all clock h chipset.
S a • Support one t pair of differential CPU clocks, one pair of a differential push-pull CPU clocks, 3 AGP and D 10 PCI.
.
• w Enhanced PCI Output Drive selectable by I2C.
•w One 48MHz clock and 24_48MHz clock via I2C.
w• Three 14.
318MHz reference clocks.
• • • • • • • Power management control to stop CPU, PCI, REF, 24_48MHz, 48MHz and AGP clocks.
Supports 2-wire I2C serial bus interface with readback.
Single byte micro-step linear Frequency Programming via I2C with glitch free smooth switching.
Built-in programmable watchdog timer up to 63 seconds with 1-second interval.
It will generate a low reset output when timer expired.
Spread Spectrum ± 0.
25% center, ± 0.
5% center, ± 0.
75% center, and 0 to -0.
5% downspread.
50% duty cycle with low jitter.
Available in 300 mil 48 Pin SSOP.
BLOCK DIAGRAM XIN XOUT XTAL OSC FS (0:4)* PLL1 SST m o .
c U 4 t e e h S a t a .
D w w w 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDD1 GND XIN XOUT VDD2 48MHz/FS2*^ 24_48MHz/FS3* ^ GND FS4*^/PCI_F SEL24_48#^/PCI0 PCI1 GND PCI2 PCI3 VDD3 PCI4 PCI5 PCI6 GND PCI7 PCI8 PCI9_E/SELPCI9_E*^ VDD3 WDRESET#^ 1 2 3 4 5 6 7 8 9 48 47 46 45 44 43 42 41 40 REF0/FS0*^ REF1/FS1*^ REF_F N/C AGP_STOP#^ GND CPUT0 CPUC0 VDDL1 CPUT_CS CPUC_CS GND CPU_STOP#^ PCI_STOP#^ PD#^ VDDL2 GND SDATA SCLK GND AGP2 AGP1 AGP0 VDD4 Note: ^: 100k internal Pull up v: 100k internal Pull down #: Active low * : Bi-directional up latched at power-up PLL205-16 POWER GROUP • • • • • • VDD1 REF(0:1) REF_F CPUT0 CPUC0 VDD1: REF(0:1), REF_F, XIN, XOUT VDD2: 48MHz or 24_48MHz VDD3: PCI(0:8), PCI9_E VDD4: AGP(0:2) VDDL1: CPUT0, CPUC0, CPUT_CS, CPUC_CS VDDL2: PLL Core VDDL1 Control Logic CPUT_CS KEY SPECIFICATIONS • • • • • CPUC_CS VDD4 AGP (0:2) VDD3 PD PCI (0:8) PCI9_E VDD2 PLL2 48MHz ÷2 SDATA...

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