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TC220E

Toshiba
Part Number TC220E
Manufacturer Toshiba
Description (TC220C/E) DRAM Core
Published Feb 19, 2006
Detailed Description TOSHIBA Toshiba’s 1 Mbit embedded DRAM core is available for the TC220C and TC220E product families. Each DRAM cell is ...
Datasheet PDF File TC220E PDF File

TC220E
TC220E

Overview
TOSHIBA Toshiba’s 1 Mbit embedded DRAM core is available for the TC220C and TC220E product families.
Each DRAM cell is based on a three transistor structure as shown in Figure 1.
This multi-feature DRAM core is easily integrated into a broad range of applications through utilization of different core configurations.
w DRAM Core Features w • Power supply: 3.
3V ±0.
3V • Memory configurations – 128K x 8 bit – 64K x 16 bit – 32K x 32 bit – 16K x 64 bit • Full address without multiplex • Separate data input and output • Read access modes – Random access – EDO/Hyper page mode • Refresh scheme – RAS only refresh – CBR (CAS before RAS) refresh • Performance specification – trc random read cycle: 50 ns – tpc page mode read cycle: 25 ns – Refresh cycle: 256 cycles/ms (@Tj = 85°C) a D .
w S a t e e h U 4 t m o .
c TC220C/E DRAM Core 0.
3µm 3T dRAMASIC Embedded DRAM Benefits Benefits derived from integration of DRAM with logic are: • Flexibility in utilizing different DRAM core configurations based on the application requirement • Memory access time lower than discrete packaged devices • Elimination of a large number of pins and associated packages, effectively reducing circuit board area • Lower power consumption since systems with fast and wide memory busses will dissipate significantly less power due to lower capacitance on-chip connections • Lower switching noise on data bus between memory and logic Target Applications Read word w w .
D w Read bit t a S a OE e h Applications for 3T dRAMASIC™ include hard disk drive controllers, buffer memory for hubs and switches and printers.
t e U 4 .
c m o O0–O15 Output Buffer Add.
Counter (CBR) WE RAS CAS Clock Generator Column Address Buffer Row Address Buffer I0–I15 Input Buffer Column Decoder Sense Amplifiers Row Decoder A0–A7 Memory Cell Array Write word Write bit A8–A15 Figure 1.
Three-Transistor DRAM Cell Figure 2.
DRAM Core Block Diagram w w w .
D a S a t e e h U 4 t m o .
c 4569-02 Product Brie...


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