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CY7C007AV

Cypress Semiconductor
Part Number CY7C007AV
Manufacturer Cypress Semiconductor
Description (CY7C006AV - CY7C145AV) Dual Port Static RAM
Published Feb 26, 2006
Detailed Description CY7C138AV CY7C139AV CY7C144AV CY7C145AV CY7C006AV CY7C016AV CY7C007AV CY7C017AV 3.3V 4K/8K/16K/32K x 8/9 Dual-Port Stati...
Datasheet PDF File CY7C007AV PDF File

CY7C007AV
CY7C007AV

Overview
CY7C138AV CY7C139AV CY7C144AV CY7C145AV CY7C006AV CY7C016AV CY7C007AV CY7C017AV 3.
3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM Features w w • True Dual-Ported memory cells which allow simultaneous access of the same memory location • 4K/8K/16K/32K x 8 organizations (CY7C0138AV/144AV/006AV/007AV) • 4K/8K/16K/32K x 9 organizations (CY7C0139AV/145AV/016AV/017AV) • 0.
35-micron CMOS for optimum speed/power • High-speed access: 20/25 ns • Low operating power — Active: ICC = 115 mA (typical) w .
D a t a e h S et 4U .
m o c CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV 3.
3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM • Fully asynchronous operation • Automatic power-down • Expandable data bus to 16/18 bits or more using Master/ Slave chip select when using more than one device • On-chip arbitration logic • Semaphores included to permit software handshaking between ports • INT flag for port-to-port communication • Pin select for Master or Slave • Commercial and Industrial Temperature Ranges • Available in 68-pin PLCC (all) and 64-pin TQFP (7C006AV & 7C144AV) — Standby: ISB3 = 10 µA (typical) Logic Block Diagram R/WL CEL OEL [1] 8/9 I/O0L–I/O7/8L A0L–A11–14L [2] 12–15 A0L–A11–14L CEL OEL R/WL SEML BUSYL INTL [3] [2] w w w Address Decode 12–15 .
D t a I/O Control S a e h t e U 4 .
c m o R/WR CER OER 8/9 [1] I/O Control I/O0R–I/O7/8R True Dual-Ported RAM Array Address Decode 12–15 12–15 [2] A0R–A11–14R Interrupt Semaphore Arbitration A0R–A11–14R CER OER R/WR SEMR [3] [2] M/S For the most recent information, visit the Cypress web site at www.
cypress.
com Notes: 1.
I/O0–I/O7 for x8 devices; I/O0–I/O8 for x9 devices.
2.
A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K devices; A0–A14 for 32K devices; 3.
BUSY is an output in master mode and an input in slave mode.
Cypress Semiconductor Corporation Document #: 38-06051 Rev.
*B • 3901 North First Street • San Jose w w • w .
D at h S a t e e BUSYR INTR 4U...


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