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HY5DU28822AT

Part Number	HY5DU28822AT
Manufacturer	Hynix Semiconductor
Description	(HY5DU28xxxAT) 3rd 128M DDR SDRAM
Published	Mar 24, 2006
Detailed Description	HY5DU28422A(L)T HY5DU28822A(L)T HY5DU281622A(L)T 3rd 128M DDR SDRAM HY5DU28422A(L)T HY5DU28822A(L)T HY5DU281622A(L)T T...
Datasheet	HY5DU28822AT PDF File

Overview

HY5DU28422A(L)T HY5DU28822A(L)T HY5DU281622A(L)T 3rd 128M DDR SDRAM HY5DU28422A(L)T HY5DU28822A(L)T HY5DU281622A(L)T This document is a general product description and is subject to change without notice.
Hynix semiconductor does not assume any responsibility for use of circuits described.
No patent licenses are implied.
Rev.
0.
4/May.
02 1 www.
DataSheet4U.
com HY5DU28422A(L)T HY5DU28822A(L)T HY5DU281622A(L)T Revision History 1.
Revision 0.
2 (Nov.
01) 1) Device operation and timing diagram removed 2) tHZ / tLZ SPEC defined 2.
Revision 0.
3 (Feb.
02) 1) “Preliminary” removed 3.
Revision 0.
4 (May.
02) 1) Input leakage current changed from +/-5uA to +/-2uA Rev.
0.
4/May.
02 2 HY5DU28422A(L)T HY5DU28822A(L)T HY5DU281622A(L)T DESCRIPTION The Hynix HY5DU28422A(L)T and HY5DU28822A(L)T and HY5DU281622A(L)T are a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth.
The Hynix 128Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock.
While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it.
The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth.
All input and output voltage levels are compatible with SSTL_2.
FEATURES • • • • • • VDD, VDDQ = 2.
5V +/- 0.
2V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) On chip DLL align DQ and DQS transition with CK transition DM mask write data-in at the both rising and falling edges of the data strobe • • • • • • • • All addresse...

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