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HY5DU28822DT

Part Number	HY5DU28822DT
Manufacturer	Hynix Semiconductor
Description	(HY5DU28xx22D(L)T) 128Mb-S DDR SDRAM
Published	Oct 9, 2006
Detailed Description	www.DataSheet4U.com HY5DU28422D(L)T HY5DU28822D(L)T HY5DU281622D(L)T 128Mb-S DDR SDRAM HY5DU28422D(L)T HY5DU28822D(L)T...
Datasheet	HY5DU28822DT PDF File

Overview

www.
DataSheet4U.
com HY5DU28422D(L)T HY5DU28822D(L)T HY5DU281622D(L)T 128Mb-S DDR SDRAM HY5DU28422D(L)T HY5DU28822D(L)T HY5DU281622D(L)T DataSheet4U.
com DataShee This document is a general product description and is subject to change without notice.
Hynix semiconductor does not assume any responsibility for use of circuits described.
No patent licenses are implied.
Rev.
0.
0/Apr.
2003 1 DataSheet4U.
com www.
DataSheet4U.
com HY5DU28422D(L)T HY5DU28822D(L)T HY5DU281622D(L)T Revision History 1.
Rev 0.
0 (Apr.
2003) 1) Datasheet Release in Preliminary version et4U.
com DataSheet4U.
com DataShee Rev.
0.
0 / Apr.
2003 2 DataSheet4U.
com www.
DataSheet4U.
com HY5DU28422D(L)T HY5DU28822D(L)T HY5DU281622D(L)T DESCRIPTION PRELIMINARY The HY5DU28422D(L)T, HY5DU28822D(L)T and HY5DU281622D(L)T are a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth.
This Hynix 128Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock.
While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it.
The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth.
All input and output voltage levels are compatible with SSTL_2.
FEATURES • • • • • • • VDD, VDDQ = 2.
6V +/- 0.
1V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) • • • • All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock Programmable /CAS latency 2 / 2.
5/ 3 supported Programmable burst length 2 / 4 / 8 with both sequential and interleave mode Internal four bank operation...

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