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MB91107

Fujitsu Media Devices
Part Number MB91107
Manufacturer Fujitsu Media Devices
Description (MB91107 / MB91108) 32-bit RISC Microcontroller
Published Oct 16, 2006
Detailed Description www.DataSheet4U.com FUJITSU SEMICONDUCTOR DATA SHEET DS07-16305-2E 32-bit RISC Microcontroller CMOS FR Series MB9110...
Datasheet PDF File MB91107 PDF File

MB91107
MB91107

Overview
www.
DataSheet4U.
com FUJITSU SEMICONDUCTOR DATA SHEET DS07-16305-2E 32-bit RISC Microcontroller CMOS FR Series MB91107/108 MB91107/108 s DESCRIPTION The MB91107 is a standard single-chip microcontroller constructed around the 32-bit RISC CPU (FR* family) core with abundant I/O resources and bus control functions optimized for high-performance/high-speed CPU processing for embedded controller applications.
To support the vast memory space accessed by the 32-bit CPU, the MB91107 normally operates in the external bus access mode and executes instructions on the internal 1 Kbyte cache memory and RAM (MB91107: 128 Kbytes, MB91108: 160 Kbytes) for enhanced performance.
The MB91107 is optimized for applications requiring high-performance CPU processing such as navigation systems, high-performance FAXs and printer controllers.
*: FR Family stands for FUJITSU RISC controller.
s FEATURES FR CPU • • • • • • 32-bit RISC, load/store architecture, 5-stage pipeline Operating clock frequency: Internal 50 MHz/external 25 MHz (PLL used at source oscillation 12.
5 MHz) General purpose registers: 32 bits × 16 16-bit fixed length instructions (basic instructions), 1 instruction/1 cycle Memory to memory transfer, bit processing, barrel shifter processing: Optimized for embedded applications Function entrance/exit instructions, multiple load/store instructions of register contents, instruction systems supporting high level languages (Continued) 120-pin Plastic LQFP s PACKAGE (FPT-120P-M21) DataSheet 4 U .
com www.
DataSheet4U.
com MB91107/108 (Continued) • Register interlock functions, efficient assembly language coding • Branch instructions with delay slots: Reduced overhead time in branch executions • Internal multiplier/supported at instruction level Signed 32-bit multiplication: 5 cycles Signed 16-bit multiplication: 3 cycles • Interrupt (push PC and PS): 6 cycles, 16 priority levels Bus interface • • • • • • Clock doubler: Internal 50 MHz, external bus 25 MHz operation 25-bit ad...


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