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MB91F128

Fujitsu Media Devices
Part Number MB91F128
Manufacturer Fujitsu Media Devices
Description (MB91F127 / MB91F128) 32-Bit Microcontroller CMOS
Published Oct 16, 2006
Detailed Description www.DataSheet4U.com FUJITSU SEMICONDUCTOR DATA SHEET DS07-16310-1E 32-Bit Microcontroller CMOS FR30 Series MB91F127/...
Datasheet PDF File MB91F128 PDF File

MB91F128
MB91F128

Overview
www.
DataSheet4U.
com FUJITSU SEMICONDUCTOR DATA SHEET DS07-16310-1E 32-Bit Microcontroller CMOS FR30 Series MB91F127/F128 s DESCRIPTION This model, designed on the basis of 32-bit RISC CPU (FR30 series), is a standard single-chip micro controller with built-in I/O resources and bus control functions.
The functions are suitable for built-in control that requires high-speed CPU processing.
MB91F127 includes 256 Kbytes built-in flash memory and 14 Kbytes built-in RAM.
MB91F128 includes 510 Kbytes built-in flash memory and 14 Kbytes built-in RAM.
The specifications of the devices are best suited for applications requiring high-level CPU processing capabilities, such as navigation system, high-performance FAX, and printer controller.
s FEATURES FR-CPU • 32-bit RISC (FR30), load/store architecture, 5-step pipeline • Operating frequency : Internal 25 MHz • General register : 32bit x 16 registers • 16-bit fixed-length instructions (primitives), 1 instruction/1 cycle • Instructions of memory-to-memory transfer, bit processing, and barrel shift : Instructions suitable for built-in control (Continued) s PACKAGE 100 pin, Plastic LQFP (FPT-100P-M05) DataSheet 4 U .
com www.
DataSheet4U.
com MB91F127/F128 • Function entry/exit instructions, multi load/store instruction for register data : High-level language compatible instructions • Register interlock functions : Simple description of assembler language • Branch instructions with delay slot : Reduced overhead on branching process • Built-in multiplier/ Supporting at instruction level Signed 32-bit multiplying : 5 cycles Signed 16-bit multiplying : 3 cycles • Interrupt (saving PC and PS) : 6 cycles, 16 priority levels Bus interface • Maximum of 25 MHz internal operation rate • 25-bit address bus (32 MB space) • 16-bit address output, 8/16-bit data input/output • Basic bus cycle : 2-clock cycle • Chip selection outputs specifiable in a minimum of 64 Kbytes steps : 6 outputs • Automatic wait cycle : Specifiable flexibly from...


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