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ZL50011

Zarlink Semiconductor
Part Number ZL50011
Manufacturer Zarlink Semiconductor
Description Flexible 512 Channel DX
Published Jan 10, 2007
Detailed Description www.DataSheet4U.com ZL50011 Flexible 512 Channel DX with on-chip DPLL Data Sheet Features • • • • • • 512 channel x 512...
Datasheet PDF File ZL50011 PDF File

ZL50011
ZL50011

Overview
www.
DataSheet4U.
com ZL50011 Flexible 512 Channel DX with on-chip DPLL Data Sheet Features • • • • • • 512 channel x 512 channel non-blocking switch at 2.
048 Mbps, 4.
096 Mbps or 8.
192 Mbps operation Rate conversion between the ST-BUS inputs and ST-BUS outputs Integrated Digital Phase-Locked Loop (DPLL) meets Telcordia GR-1244-CORE Stratum 4 specifications DPLL provides reference monitor, jitter attenuation and free run functions Per-stream ST-BUS input with data rate selection of 2.
048 Mbps, 4.
096 Mbps or 8.
192 Mbps Per-stream ST-BUS output with data rate selection of 2.
048 Mbps, 4.
096 Mbps or 8.
192 Mbps; the output data rate can be different than the input data rate Per-stream high impedance control output for every ST-BUS output with fractional bit advancement Per-stream input channel and input bit delay programming with fractional bit delay Ordering Information ZL50011/QCC ZL50011/GDC 160 Pin LQFP 144 Ball LBGA July 2005 • • • • • • • • • • VSS Per-stream output channel and output bit delay programming with fractional bit advancement Multiple frame pulse outputs and reference clock outputs Per-channel constant throughput delay Per-channel high impedance output control Per-channel message mode Per-channel Pseudo Random Bit Sequence (PRBS) pattern generation and bit error detection Control interface compatible to Motorola nonmultiplexed CPUs Connection memory block programming capability IEEE-1149.
1 (JTAG) test port 3.
3 V I/O with 5 V tolerant input RESET ODE • • VDD STi0-15 S/P Converter Data Memory P/S Converter STo0-15 FPi CKi Input Timing Connection Memory Output HiZ Control STOHZ0-15 REF DPLL Microprocessor Interface and Internal Output Timing FPo0 CKo0 FPo1 CKo1 FPo2 CKo2 Registers OSC APLL Test Port IC0 - 4 CLKBYPS ICONN1 VDD_APLL VSS_APLL DTA D15 - 0 A11 - 0 XTALo XTALi Figure 1 - ZL50011 Functional Block Diagram Zarlink Semiconductor US Patent No.
5,602,884, UK Patent No.
0772912, France Brevete S.
G.
D.
G.
0772912; Germany DBP ...


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