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ZL50020

Zarlink Semiconductor
Part Number ZL50020
Manufacturer Zarlink Semiconductor
Description Enhanced 2 K Digital Switch
Published Mar 31, 2007
Detailed Description www.DataSheet4U.com ZL50020 Enhanced 2 K Digital Switch Data Sheet Features • 2048 channel x 2048 channel non-blocking ...
Datasheet PDF File ZL50020 PDF File

ZL50020
ZL50020

Overview
www.
DataSheet4U.
com ZL50020 Enhanced 2 K Digital Switch Data Sheet Features • 2048 channel x 2048 channel non-blocking digital Time Division Multiplex (TDM) switch at 8.
192 Mbps and 16.
384 Mbps or using a combination of ports running at 2.
048, 4.
096, 8.
192 and 16.
384 Mbps 32 serial TDM input, 32 serial TDM output streams Output streams can be configured as bidirectional for connection to backplanes Exceptional input clock cycle to cycle variation tolerance (20 ns for all rates) Per-stream input and output data rate conversion selection at 2.
048, 4.
096, 8.
192 or 16.
384 Mbps.
Input and output data rates can differ Per-stream high impedance control outputs (STOHZ) for 16 output streams Per-stream input bit delay with flexible sampling point selection Per-stream output bit and fractional bit advancement • • • • • • • O rdering Information ZL50020GAC ZL50020QCC ZL50020QCG1 ZL50020GAG2 256 Ball PBGA 256 Lead LQFP 256 Lead LQFP* 256 Ball PBGA** Trays Trays Trays, Bake & Drypack Trays, Bake & Drypack November 2006 • • • • • • • *Pb Free Matte Tin **Pb Free Tin/Silver/Copper -40 ° C to +85 ° C Per-channel ITU-T G.
711 PCM A-Law/µ-Law Translation Four frame pulse and four reference clock outputs Three programmable delayed frame pulse outputs Input clock: 4.
096 MHz, 8.
192 MHz, 16.
384 MHz Input frame pulses:61 ns, 122 ns, 244 ns Per-channel constant or variable throughput delay for frame integrity and low latency applications Per Stream (32) Bit Error Rate Test circuits complying to ITU-O.
151 VSS RESET ODE VDD_CORE VDD_IO VDD_COREA VDD_IOA STi[31:0] FPi CKi MODE_4M0 MODE_4M1 S/P Converter Data Memory P/S Converter STio[31:0] Input Timing Connection Memory Output HiZ Control STOHZ[15:0] Output Timing FPo[3:0] CKo[3:0] FPo_OFF[2:0] Internal Registers & Microprocessor Interface Test Port D[15:0] DS_RD A[13:0] R/W_WR Figure 1 - ZL50020 Functional Block Diagram 1 Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarli...


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