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ZL30102

Zarlink Semiconductor
Part Number ZL30102
Manufacturer Zarlink Semiconductor
Description T1/E1 Stratum 4/4E Redundant System Clock Synchronizer
Published Mar 27, 2007
Detailed Description ZL30102 T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110 Data Sheet Features • Synchronizes ...
Datasheet PDF File ZL30102 PDF File

ZL30102
ZL30102

Overview
ZL30102 T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.
110 Data Sheet Features • Synchronizes to clock-and-sync-pair to maintain minimal phase skew between an H.
110 primary master clock and a secondary master clock • Supports Telcordia GR-1244-CORE Stratum 4 and 4E • Supports ITU-T G.
823 and G.
824 for 2048 kbit/s and 1544 kbit/s interfaces • Supports ANSI T1.
403 and ETSI ETS 300 011 for ISDN primary rate interfaces • Simple hardware control interface • Manual and Automatic hitless reference switching between any combination of valid input reference frequencies • Accepts three input references and synchronizes to any combination of 8 kHz, 1.
544 MHz, 2.
048 MHz, 8.
192 MHz or 16.
384 MHz inputs • Provides a range of clock outputs: 1.
544 MHz, 2.
048 MHz, 3.
088 MHz, 6.
312 MHz, 16.
384 MHz and either 4.
096 MHz and 8.
192 MHz or 32.
768 MHz and 65.
536 MHz • Provides 5 styles of 8 kHz framing pulses • Holdover frequency accuracy of 1x10-7 April 2010 Ordering Information ZL30102QDG1 64 pin TQFP* Trays, Bake & Drypack *Pb Free Matte Tin -40°C to +85°C • Provides Lock, Holdover and selectable Out of Range indication • Attenuates wander from 1.
8 Hz • Less than 0.
6 nspp intrinsic jitter on all output clocks • External master clock source: Clock Oscillator or Crystal Applications • Synchronization and timing control for multi-trunk DS1/ E1 terminal systems such as DSLAMs, Gateways and PBXs • Clock and frame pulse source for H.
110 CT Bus, ST-BUS, GCI and other time division multiplex (TDM) buses REF0 REF1 REF2 REF2_SYNC REF_FAIL0 REF_FAIL1 REF_FAIL2 OOR_SEL REF_SEL1:0 RST OSCi OSCo TIE_CLR FASTLOCK LOCK OUT_SEL Master Clock MUX TIE Corrector Circuit Virtual Reference DPLL E1 Synthesizer Reference Monitor TIE Corrector Enable State Machine Mode Control Frequency Select MUX DS1 Synthesizer DS2 Synthesizer IEEE 1149.
1a C2o C4/C65o C8/C32o C16o F4/F65o F8/F32o F16o C1.
5o C3o C6o TRST MODE_SEL1:0 SEC_MSTR HMS HOLDOVER TCK TDI TMS TDO Figure 1 - Fu...


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