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HYB39S256160T

Siemens Semiconductor
Part Number HYB39S256160T
Manufacturer Siemens Semiconductor
Description (HYB39S256xxx) 256 MBit Synchronous DRAM
Published Jun 10, 2007
Detailed Description 256 MBit Synchronous DRAM HYB 39S256400/800/160T Preliminary Information • High Performance: -8 -8B 100 10 6 12 7 -10 ...
Datasheet PDF File HYB39S256160T PDF File

HYB39S256160T
HYB39S256160T

Overview
256 MBit Synchronous DRAM HYB 39S256400/800/160T Preliminary Information • High Performance: -8 -8B 100 10 6 12 7 -10 100 10 7 15 8 Units MHz ns ns ns ns • Multiple Burst Read with Single Write Operation • Automatic and Controlled Precharge Command • Data Mask for Read/Write control (× 4, × 8) • Data Mask for byte control (× 16) • Auto Refresh (CBR) and Self Refresh • Suspend Mode and Power Down Mode • 8192 refresh cycles/64 ms 7,8 µ • Random Column Address every CLK (1-N Rule) • Single 3.
3 V ± 0.
3 V Power Supply • LVTTL Interface versions • Plastic Packages: P-TSOPII-54 400mil width (× 4, × 8, × 16) • -8 part for PC100 2-2-2 operation -8B part for PC100 3-2-3 operation -10 part for PC66 2-2-2 operation fCK tCK3 tAC3 tCK2 tAC2 • • • • www.
DataSheet4U.
com 125 8 6 10 6 Fully Synchronous to Positive Clock Edge 0 to 70 °C operating temperature Four Banks controlled by BA0 & BA1 Programmable CAS Latency: 2, 3, 4 • Programmable Wrap Sequence: Sequential or Interleave • Programmable Burst Length: 1, 2, 4, 8 The HYB 39S256400/800/160T are four bank Synchronous DRAM’s organized as 4 banks × 16 MBit × 4, 4 banks × 8 MBit × 8 and 4 banks × 4 MBit × 16 respectively.
These synchronous devices achieve high speed data transfer rates for CAS latencies by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock.
The chip is fabricated with SIEMENS’ advanced 256 MBit DRAM process technology.
The device is designed to comply with all JEDEC standards set for synchronous DRAM products, both electrically and mechanically.
All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur at higher rate than is possible with standard DRAMs.
A sequential and gapless data rate of is possible depending on burst length, CAS latency and speed grade of the device.
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