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MT8930C

Mitel Networks
Part Number MT8930C
Manufacturer Mitel Networks
Description Subscriber Network Interface Circuit
Published Jun 20, 2007
Detailed Description ® CMOS ST-BUS™ FAMILY MT8930C Subscriber Network Interface Circuit Preliminary Information Features • • • • • • • • • ...
Datasheet PDF File MT8930C PDF File

MT8930C
MT8930C



Overview
® CMOS ST-BUS™ FAMILY MT8930C Subscriber Network Interface Circuit Preliminary Information Features • • • • • • • • • • • • • • www.
DataSheet4U.
com ISSUE 1 May 1995 ETS 300-012, CCITT I.
430 and ANSI T1.
605 S/T interface Full-duplex 2B+D, 192 kbit/s transmission Link activation/deactivation D-channel access contention resolution Point-to-point, point-to-multipoint and star configurations Master (NT)/Slave (TE) modes of operation Exceeds loop length requirements Complete loopback testing capabilities On chip HDLC D-channel protocoller 8 bit Motorola/Intel microprocessor interface Controllerless or microprocessor-controlled operation Mitel ST-BUS interface Low power CMOS technology Single 5 volt power supply Ordering Information MT8930CC 28 Pin Ceramic DIP MT8930CE 28 Pin Plastic DIP MT8930CP 44 Pin PLCC -40°C to +85°C Description The MT8930C Subscriber Network Interface Circuit (SNIC) implements the ETSI ETS 300-012, CCITT I.
430 and ANSI T1.
605 Recommendations for the ISDN S and T reference points.
Providing point-topoint and point-to-multipoint digital transmission, the SNIC may be used at either end of the subscriber line (NT or TE).
An HDLC D-channel protocoller is included and controlled through a Motorola/Intel microprocessor port.
A controllerless mode allows the SNIC to operate without a microprocessor.
The MT8930C is fabricated in Mitel’s CMOS process.
Applications • • • • • ISDN NT1 ISDN S or T interface ISDN Terminal Adaptor (TA) Digital sets (TE1) - 4 wire ISDN interface Digital PABXs, Digital Line Cards (NT2) DSTi DSTo ST-BUS Interface D-channel Priority Mechanism LTx S-Bus Link Interface VBias LRx F0od C4b F0b STAR/Rsto CK/NT Cmode Microprocessor Interface VSS Timing and Control PLL HDLC Transceiver Link Activation Controller VDD Rsti HALF AD0-7 R/W/WR, AFT/PRI DS/RD, DinB AS/ALE, P/SC CS, DReq IRQ/NDA, DCack Figure 1 - Functional Block Diagram 9-35 MT8930C Preliminary Information NC NC F0b C4b HALF NC VDD VBias LTx NC LRx F0od DS...



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