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MITSUBISHI SEMICONDUCTOR <TRANSISTOR ARRAY>
IMIN PREL
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M63850P/FP
4-UNIT 1. 5A DMOS ARRAY WITH CLAMP DIODE
PIN CONFIGURATION
COM 1 O1← 2 IN1→ 3 GND 16 →O4 15 ←IN4 14 VDD 13 12
DESCRIPTION The M63850P/FP is a inverter input power DMOS transistor array that consists of 4 independent output N-channel DMOS transistors.
4 5
GND
FEATURES 4 circuits of N-channels DMOS High breakdown voltage (VDS ≥ 80V) High-current driving (IDS(max) = 1. 5A) With clamping diodes Drain-source on-state low resistance (RON = 0. 72Ω, @ = 1. 25A) Wide operating temperature range (Ta = –40 to +85°C)
IN2→ 6 NC 7 O2← 8
11 ←IN3 10 →O3 9 COM NC : No connection
Package type 16P4(P) 16P2N(FP)
CIRCUIT DIAGRAM
VDD COM OUTPUT 30k INPUT 4. 2k
APPLICATION Drives of relays and printers, digit drives of indication elements (LEDs and lamps)
GND The four circuits share the COM and GND.
FUNCTION The M63850P/FP is consists of 4 independent N-channel DMOS transistors. Each DMOS transistor is connected in a common-source with GND PIN. The clamp diodes for spike killers are connected between the output pin and the COM pin of each DMOS transistor. The maximum of Drain current is 1. 5A. The maximum Drain-Source voltage is 80V.
The diode, indicated with the dotted line, is parasitic, and cannot be used. Unit : Ω
ABSOLUTE MAXIMUM RATINGS
Symbol VDD VDS IDS VI VR IF Pd Topr Tstg Parameter Supply voltage Drain-source voltage Drain current Input voltage
(Unless otherwise noted, Ta = –40 ~ +85°C)
Conditions Output, H Current per circuit output, L
Ratings 7 –0. 5 ~ +80 1. 5 –0. 5 ~ VDD 80 1. 5 1. 47(P)/1. 00(FP) –40 ~ +85 –55 ~ +125
Unit V V A V V A W °C °C
Apr. 2005
Clamping diode reverse voltage Clamping diode forward current Power dissipation Operating temperature Storage temperature
Ta = 25°C, when mounted on board
MITSUBISHI SEMICONDUCTOR <TRANSISTOR ARRAY>
IMIN PREL
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M63850FP PDF File
