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CY7C1475V25

Cypress Semiconductor
Part Number CY7C1475V25
Manufacturer Cypress Semiconductor
Description (CY7C147xV25) 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
Published Nov 10, 2007
Detailed Description www.DataSheet4U.com PRELIMINARY CY7C1471V25 CY7C1473V25 CY7C1475V25 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SR...
Datasheet PDF File CY7C1475V25 PDF File

CY7C1475V25
CY7C1475V25

Overview
www.
DataSheet4U.
com PRELIMINARY CY7C1471V25 CY7C1473V25 CY7C1475V25 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL™ Architecture Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles.
• Can support up to 133-MHz bus operations with zero wait states • Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through operation • Byte Write capability • 2.
5V/1.
8V I/O power supply • Fast clock-to-output times — 6.
5 ns (for 133-MHz device) — 8.
5 ns (for 100-MHz device) • Clock Enable (CEN) pin to enable clock and suspend operation • Synchronous self-timed writes • Asynchronous Output Enable • Offered in JEDEC-standard lead-free 100 TQFP, and 165-ball fBGA packages for CY7C1471V25 and CY7C1473V25.
209-ball fBGA package for CY7C1475V25.
• Three chip enables for simple depth expansion.
• Automatic Power-down feature available using ZZ mode or CE deselect.
• JTAG boundary scan for BGA and fBGA packages • Burst Capability—linear or interleaved burst order • Low standby power Functional Description[1] The CY7C1471V25, CY7C1473V25 and CY7C1475V25 are 2.
5V, 2M x 36/4M x 18/1M x 72 Synchronous Flow-through Burst SRAMs designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states.
The CY7C1471V25, CY7C1473V25 and CY7C1475V25 are equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle.
This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions.
All synchronous inputs pass through input registers controlled by the rising edge of the clock.
The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends opera...


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