DatasheetsPDF.com

CY7C1475V33

Cypress Semiconductor
Part Number CY7C1475V33
Manufacturer Cypress Semiconductor
Description (CY7C147xV33) 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
Published Nov 10, 2007
Detailed Description www.DataSheet4U.com CY7C1471V33 CY7C1473V33 CY7C1475V33 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL™...
Datasheet PDF File CY7C1475V33 PDF File

CY7C1475V33
CY7C1475V33


Overview
www.
DataSheet4U.
com CY7C1471V33 CY7C1473V33 CY7C1475V33 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL™ Architecture Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Supports up to 133 MHz bus operations with zero wait states • Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self timed output buffer control to eliminate the need to use OE • Registered inputs for flow through operation • Byte Write capability • 3.
3V/2.
5V IO supply (VDDQ) • Fast clock-to-output times — 6.
5 ns (for 133-MHz device) • Clock Enable (CEN) pin to enable clock and suspend operation • Synchronous self timed writes • Asynchronous Output Enable (OE) • CY7C1471V33, CY7C1473V33 available in JEDEC-standard Pb-free 100-Pin TQFP, Pb-free and non-Pb-free 165-Ball FBGA package.
CY7C1475V33 available in Pb-free and non-Pb-free 209-Ball FBGA package • Three Chip Enables (CE1, CE2, CE3) for simple depth expansion • Automatic power down feature available using ZZ mode or CE deselect • IEEE 1149.
1 JTAG Boundary Scan compatible • Burst Capability — linear or interleaved burst order • Low standby power Functional Description [1] The CY7C1471V33, CY7C1473V33 and CY7C1475V33 are 3.
3V, 2M x 36/4M x 18/1M x 72 synchronous flow through burst SRAMs designed specifically to support unlimited true back-to-back read or write operations without the insertion of wait states.
The CY7C1471V33, CY7C1473V33 and CY7C1475V33 are equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive read or write operations with data being transferred on every clock cycle.
This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent write-read transitions.
All synchronous inputs pass through input registers controlled by the rising edge of the clock.
The clock input is qualified by the Clock Enable (CEN) signal, which when...


Similar Datasheet


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)