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IS61NLP25636A

Part Number	IS61NLP25636A
Manufacturer	ISSI
Description	9Mb STATE BUS SRAM
Published	Jul 12, 2008
Detailed Description	IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A 256K x 36 and 512K x 18 9Mb, PIPELINE 'NO WAIT' STATE BUS SRAM ...
Datasheet	IS61NLP25636A PDF File

Overview

IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A 256K x 36 and 512K x 18 9Mb, PIPELINE 'NO WAIT' STATE BUS SRAM AUGUST 2014 FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control us- ing MODE input • Three chip enables for simple depth expansion and address pipelining • Power Down mode • Common data inputs and data outputs • CKE pin to enable clock and suspend operation • JEDEC 100-pin TQFP, 165-ball PBGA and 119-ball PBGA packages • Power supply: NVP: Vdd 2.
5V (± 5%), Vddq 2.
5V (± 5%) NLP: Vdd 3.
3V (± 5%), Vddq 3.
3V/2.
5V (± 5%) • JTAG Boundary Scan for PBGA packages • Industrial temperature available • Lead-free available DESCRIPTION The 9 Meg 'NLP/NVP' product family feature high-speed, low-power synchronous static RAMs designed to provide a bur...

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