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ICS83023I

Part Number	ICS83023I
Manufacturer	Integrated Circuit Systems
Description	DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
Published	Dec 18, 2008
Detailed Description	Integrated Circuit Systems, Inc. ICS83023I DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR /BUFFER Features • Two LVCMOS...
Datasheet	ICS83023I PDF File

Overview

Integrated Circuit Systems, Inc.
ICS83023I DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR /BUFFER Features • Two LVCMOS / LVTTL outputs • Two differential CLKx, nCLKx input pairs • CLK, nCLK pairs can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Maximum output frequency: 350MHz (typical) • Output skew: 60ps (maximum) • Part-to-part skew: 500ps (maximum) • Additive phase jitter, RMS: 0.
14ps (typical) • Small 8 lead SOIC package saves board space • 3.
3V operating supply • -40°C to 85°C ambient operating temperature • Available in both standard and lead-free RoHS-compliant packages GENERAL DESCRIPTION The ICS83023I is a dual, 1-to-1 Differential-toLVCMOS Translator/Fanout Buffer and a memHiPerClockS™ ber of the HiPerClockS™ family of High Performance Clock Solutions from ICS.
The differential inputs can accept most differential signal types (LVDS, LVHSTL, LVPECL, SSTL, and HCSL) and translate into two single-ended LVCMOS outputs.
The small 8-lead SOIC footprint makes this device ideal for use in applications with limited board space.
www.
DataSheet4U.
com IC S BLOCK DIAGRAM CLK0 nCLK0 CLK1 nCLK1 Q0 PIN ASSIGNMENT CLK0 nCLK0 nCLK1 CLK1 1 2 3 4 8 7 6 5 VDD Q0 Q1 GND Q1 ICS83023I 8-Lead SOIC 3.
8mm x 4.
8mm x 1.
47mm package body M Package Top View 83023AMI www.
icst.
com/products/hiperclocks.
html 1 REV.
B JANUARY 18, 2006 Integrated Circuit Systems, Inc.
ICS83023I DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR /BUFFER Type Input Input Input Input Power Output Output Power Pullup Pullup Description Inver ting differential clock input.
Inver ting differential clock input.
Power supply ground.
Single clock output.
LVCMOS / LVTTL interface levels.
Single clock output.
LVCMOS / LVTTL interface levels.
Positive supply pin.
TABLE 1.
PIN DESCRIPTIONS Number 1 2 3 4 5 www.
DataSheet4U.
com 6 Name CLK0 nCLK0 nCLK1 CLK1 GND Q1 Q0 VDD Pulldown Non-inver ting differential clock input.
Pulldown Non-inver ting differential clock input.
7 8 ...

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