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PLL520-09

PhaseLink Corporation
Part Number PLL520-09
Manufacturer PhaseLink Corporation
Description (PLL520-0x) Low Phase Noise VCXO
Published Feb 6, 2009
Detailed Description PLL520-05/-06/-07/-08/-09 www.DataSheet4U.com Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal) PIN CONF...
Datasheet PDF File PLL520-09 PDF File

PLL520-09
PLL520-09

Overview
PLL520-05/-06/-07/-08/-09 www.
DataSheet4U.
com Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal) PIN CONFIGURATION (Top View) VDD XIN XOUT SEL3^ SEL2^ OE VCON GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SEL0^ SEL1^ GND CLKC VDD CLKT GND GND FEATURES • • 100MHz to 200MHz Fundamental Mode Crystal.
Output range: 100 – 200MHz (no multiplication), 200 – 400MHz (2x multiplier), 400 – 800MHz (4x multiplier), or 800MHz – 1GHz (PLL520-09 TSSOP only, 8x multiplier).
High yield design supports up to 2pF stray capacitance at 200MHz.
CMOS (Standard drive PLL520-07 or Selectable Drive PLL520-06), PECL (Enable low PLL520-08 or Enable high PLL520-05) or LVDS output (PLL520-09).
Integrated variable capacitors.
Supports 3.
3V-Power Supply.
Available in 16-Pin (TSSOP or 3x3mm QFN) Note: PLL520-06 only available in 3x3mm.
Note: PLL520-07 only available in TSSOP.
PLL 520-0x • • • • • GND/DRIVSEL* SEL0^ 10 GND GND BLOCK DIAGRAM SEL OE VCON Oscillator XIN XOUT Amplifier w/ integrated varicaps PLL (Phase Locked Loop) ^: Internal pull-up *: PLL520-06 pin 12 is output drive select (DRIVSEL) (0 for High Drive CMOS, 1 for Standard Drive CMOS) OUTPUT ENABLE LOGICAL LEVELS Part # PLL520-08 PLL520-05 PLL520-06 PLL520-07 PLL520-09 OE State Q Q 0 (Default) 1 0 1 (Default) VCON Output enabled Tri-state Tri-state Output enabled PLL by-pass OE input: Logical states defined by PECL levels for PLL520-08 Logical states defined by CMOS levels for PLL520-05/-06/07/-09 47745 Fremont Blvd.
, Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.
phaselink.
com Rev 09/20/04 Page 1 GND The PLL520-05/-06/-07/-08/-09 is a family of VCXO ICs specifically designed to pull high frequency fundamental crystals.
Their design was optimized to tolerate higher limits of interelectrode capacitance and bonding capacitance to improve yield.
They achieve very low current into the crystal resulting in better overall stability.
Their internal varicaps allow an on chip frequency pulli...


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