DatasheetsPDF.com

PLL520-10

PhaseLink Corporation
Part Number PLL520-10
Manufacturer PhaseLink Corporation
Description Low Phase Noise VCXO
Published Feb 6, 2009
Detailed Description PLL520-10 www.DataSheet4U.com Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal) DIE CONFIGURATION OUTSEL0...
Datasheet PDF File PLL520-10 PDF File

PLL520-10
PLL520-10

Overview
PLL520-10 www.
DataSheet4U.
com Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal) DIE CONFIGURATION OUTSEL0^ 65 mil FEATURES • • • • • • • • 65MHz to 130MHz Fundamental Mode Crystal.
Output range: 65MHz – 800MHz (selectable 1x, 2x, 4x and 8x multipliers).
Low Injection Power for crystal 50uW.
Available outputs: PECL, LVDS, or CMOS (High Drive (30mA) or Standard Drive (10mA) output).
Integrated variable capacitors.
Supports 3.
3V-Power Supply.
Available in die form.
Thickness 10 mil.
OUTSEL1^ SEL0^ SEL1^ VDD VDD VDD VDD (1550,1475) 17 16 25 24 23 22 21 20 19 18 GNDBUF CMOS LVDSB PECLB VDDBUF VDDBUF PECL LVDS OE_SEL^ XIN XOUT SEL3^ 62 mil 26 27 Die ID: A1313-13A 15 28 14 13 SEL2^ OE CTRL VCON 29 12 DESCRIPTION PLL520-10 is a VCXO IC specifically designed to pull frequency fundamental crystals from 65MHz to 130MHz, with an integrated Phase Locked Loop for selectable 1x (no PLL), 2x, 4x or 8x multipliers.
Its design was optimized to tolerate higher limits of interelectrode capacitance and bonding capacitance to improve yield.
It achieves very low current into the crystal resulting in better overall stability.
Its internal varicaps allow an on chip frequency pulling, controlled by the VCON input.
11 30 C502A 31 1 2 3 4 5 6 7 8 10 9 Y (0,0) X DIE SPECIFICATIONS Name Size Reverse side Pad dimensions Thickness Value 62 x 65 mil GND 80 micron x 80 micron 10 mil BLOCK DIAGRAM SEL OE VCON Oscillator Amplifier w/ X+ integrated varicaps XPLL (Phase Locked Loop) OUTPUT SELECTION AND ENABLE OUTSEL1 (Pad #18) 0 0 1 1 OUTSEL0 ( Pad #25 ) 0 1 0 1 OE_CTRL (Pad #30) 0 1 (Default) 0 (Default) 1 Tri-state Output enabled Output enabled Tri-state Selected Output High Drive CMOS Standard CMOS LVDS PECL (default) State Q Q PLL by-pass PLL520-10 OE_SELECT (Pad #9) 0 1 (Default) Pad #9: Bond to GND to set to “0”, bond to VDD to set to “1” Pad #30: Logical states defined by PECL levels if OE_SELECT (pad #9) is “1” Logical states defined by...


Similar Datasheet


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)