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MSC8112

Freescale Semiconductor
Part Number MSC8112
Manufacturer Freescale Semiconductor
Description Dual Core Digital Signal Processor
Published Jan 7, 2010
Detailed Description Freescale Semiconductor Data Sheet Document Number: MSC8112 Rev. 0, 5/2008 MSC8112 FC-PBGA–431 20 mm × 20 mm Dual Cor...
Datasheet PDF File MSC8112 PDF File

MSC8112
MSC8112

Overview
Freescale Semiconductor Data Sheet Document Number: MSC8112 Rev.
0, 5/2008 MSC8112 FC-PBGA–431 20 mm × 20 mm Dual Core Digital Signal Processor • Two StarCore® SC140 DSP extended cores, each with an SC140 DSP core, 224 Kbyte of internal SRAM M1 memory (448 Kbyte total), 16 way 16 Kbyte instruction cache (ICache), four-entry write buffer, external cache support, programmable interrupt controller (PIC), local interrupt controller (LIC), and low-power Wait and Stop processing modes.
• 475 Kbyte M2 memory for critical data and temporary data buffering.
• 4 Kbyte boot ROM.
• M2-accessible multi-core MQBus connecting the M2 memory to both cores, operating at the core frequency, with data bus access of up to 128-bit reads and up to 64-bit writes, central efficient round-robin arbiter for core access to the bus, and atomic operation control of M2 memory access by the cores and the local bus.
• Internal PLL configured are reset by configuration signal values.
• 60x-compatible system bus with 64 or 32 bit data and 32-bit address bus, support for multi-master designs, four-beat burst transfers (eight-beat in 32-bit data mode), port size of 64/32/16/8 bits controlled by the internal memory controller,.
access to external memory or peripherals, access by an external host to internal resources, slave support with direct access to internal resources including M1 and M2 memories, and on-device arbitration for up to four master devices.
www.
DataSheet4U.
com • Direct slave interface (DSI) using a 32/64-bit slave host interface with 21–25 bit addressing and 32/64-bit data transfers, direct access by an external host to internal and external resources, synchronous or asynchronous accesses with burst capability in synchronous mode, dual or single strobe mode, write and read buffers to improve host bandwidth, byte enable signals for 1/2/4/8-byte write granularity, sliding window mode for access using a reduced number of address pins, chip ID decoding to allow one CS signal to control mu...


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