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GS8160V18AT

GSI Technology
Part Number GS8160V18AT
Manufacturer GSI Technology
Description 1M x 18 512K x 32 512K x 36 18Mb Sync Burst SRAMs
Published Apr 4, 2010
Detailed Description Preliminary www.DataSheet4U.com GS8160V18/32/36AT-350/333/300/250/200/150 100-Pin TQFP Commercial Temp Industrial Temp ...
Datasheet PDF File GS8160V18AT PDF File

GS8160V18AT
GS8160V18AT

Overview
Preliminary www.
DataSheet4U.
com GS8160V18/32/36AT-350/333/300/250/200/150 100-Pin TQFP Commercial Temp Industrial Temp Features 1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs 350 MHz–150 MHz 1.
8 V VDD 1.
8 V I/O • FT pin for user-configurable flow through or pipeline operation • Single Cycle Deselect (SCD) operation • 1.
8 V +10%/–10% core power supply • 1.
8 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating mode pins • Default to Interleaved Pipeline mode • Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle • Automatic power-down for portable applications • JEDEC-standard 100-lead TQFP package cycles can be initiated with either ADSP or ADSC inputs.
In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV.
The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input.
The Burst function need not be used.
New addresses can be loaded on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads The function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14).
Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register.
Holding FT high places the RAM in Pipeline mode, activating the rising-edgetriggered Data Output Register.
Functional Description Applications The GS8160V18/32/36AT is an 18,874,368-bit (16,777,216-bit for x32 version) high performance synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.
Byte Write and Global Write Byte write operation is performed by using Byte Write enable (BW) input combined with o...


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