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PCA9511A

NXP Semiconductors
Part Number PCA9511A
Manufacturer NXP Semiconductors
Description Hot swappable I2C-bus and SMBus bus buffer
Published Apr 27, 2010
Detailed Description PCA9511A Rev. 01 — 15 August 2005 www.DataSheet4U.com Hot swappable I2C-bus and SMBus bus buffer Product data sheet 1...
Datasheet PDF File PCA9511A PDF File

PCA9511A
PCA9511A

Overview
PCA9511A Rev.
01 — 15 August 2005 www.
DataSheet4U.
com Hot swappable I2C-bus and SMBus bus buffer Product data sheet 1.
General description The PCA9511A is a hot swappable I2C-bus and SMBus buffer that allows I/O card insertion into a live backplane without corrupting the data and clock buses.
Control circuitry prevents the backplane from being connected to the card until a stop command or bus idle occurs on the backplane without bus contention on the card.
When the connection is made, the PCA9511A provides bidirectional buffering, keeping the backplane and card capacitances isolated.
The PCA9511A rise time accelerator circuitry allows the use of weaker DC pull-up currents while still meeting rise time requirements.
The PCA9511A incorporates a digital ENABLE input pin, which enables the device when asserted HIGH and forces the device into a low current mode when asserted LOW, and an open-drain READY output pin, which indicates that the backplane and card sides are connected together (HIGH) or not (LOW).
During insertion, the PCA9511A SDA and SCL lines are precharged to 1 V to minimize the current required to charge the parasitic capacitance of the chip.
2.
Features s Bidirectional buffer for SDA and SCL lines increases fan out and prevents SDA and SCL corruption during live board insertion and removal from multi-point backplane systems s Compatible with I2C-bus standard mode, I2C-bus fast mode, and SMBus standards s Built-in ∆V/∆t rise time accelerators on all SDA and SCL lines (0.
6 V threshold) s Active HIGH ENABLE input s Active HIGH READY open-drain output s High-impedance SDA and SCL pins for VCC = 0 V s 1 V precharge on all SDA and SCL lines s Supporting clock stretching and multiple master arbitration/synchronization s Operating power supply voltage range: 2.
7 V to 5.
5 V s 0 kHz to 400 kHz clock frequency s ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 s Latch-up testing is done to JEDEC Standard...


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