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PCA9510A

NXP Semiconductors
Part Number PCA9510A
Manufacturer NXP Semiconductors
Description Hot swappable I2C-bus and SMBus bus buffer
Published Apr 28, 2010
Detailed Description PCA9510A Hot swappable I2C-bus and SMBus bus buffer Rev. 04 — 18 August 2009 Product data sheet 1. General descripti...
Datasheet PDF File PCA9510A PDF File

PCA9510A
PCA9510A


Overview
PCA9510A Hot swappable I2C-bus and SMBus bus buffer Rev.
04 — 18 August 2009 Product data sheet 1.
General description The PCA9510A is a hot swappable I2C-bus and SMBus buffer that allows I/O card insertion into a live backplane without corrupting the data and clock buses.
Control circuitry prevents the backplane from being connected to the card until a stop command or bus idle occurs on the backplane without bus contention on the card.
When the connection is made, the PCA9510A provides bidirectional buffering, keeping the backplane and card capacitances isolated.
The PCA9510A has no rise time accelerator circuitry to prevent interference when there are multiple devices in the same system.
The PCA9510A incorporates a digital ENABLE input pin, which enables the device when asserted HIGH and forces the device into a Low current mode when asserted LOW, and an open-drain READY output pin, which indicates that the backplane and card sides are connected together (HIGH) or not (LOW).
During insertion, the PCA9510A SDAIN and SCLIN pins (inputs only) are precharged to 1 V to minimize the current required to charge the parasitic capacitance of the chip.
Remark: The dynamic offset design of the PCA9510A/11A/12A/13A/14A I/O drivers allow them to be connected to another PCA9510A/11A/12A/13A/14A device in series or in parallel and to the A side of the PCA9517.
The PCA9510A/11A/12A/13A/14A cannot connect to the static offset I/Os used on the PCA9515/15A/16/16A/18 or PCA9517 B side or P82B96 Sx/y side.
2.
Features I Bidirectional buffer for SDA and SCL lines increases fan-out and prevents SDA and SCL corruption during live board insertion and removal from multipoint backplane systems I Compatible with Standard-mode I2C-bus, Fast-mode I2C-bus, and SMBus standards I Active HIGH ENABLE input I Active HIGH READY open-drain output I High-impedance SDAn and SCLn pins for VCC = 0 V I 1 V precharge on SDAIN and SCLIN inputs I Supports clock stretching and multiple master arbitration an...


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