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74AUP1G02

NXP
Part Number 74AUP1G02
Manufacturer NXP
Description Low-power 2-input NOR gate
Published Jun 12, 2010
Detailed Description 74AUP1G02 Low-power 2-input NOR gate Rev. 01 — 18 July 2005 www.DataSheet4U.com Product data sheet 1. General descrip...
Datasheet PDF File 74AUP1G02 PDF File

74AUP1G02
74AUP1G02

Overview
74AUP1G02 Low-power 2-input NOR gate Rev.
01 — 18 July 2005 www.
DataSheet4U.
com Product data sheet 1.
General description The 74AUP1G02 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.
8 V to 3.
6 V.
This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.
8 V to 3.
6 V.
This device is fully specified for partial Power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
The 74AUP1G02 provides the single 2-input NOR function.
2.
Features s Wide supply voltage range from 0.
8 V to 3.
6 V s High noise immunity s Complies with JEDEC standards: x JESD8-12 (0.
8 V to 1.
3 V) x JESD8-11 (0.
9 V to 1.
65 V) x JESD8-7 (1.
2 V to 1.
95 V) x JESD8-5 (1.
8 V to 2.
7 V) x JESD8-B (2.
7 V to 3.
6 V) s ESD protection: x HBM JESD22-A114-C exceeds 2000 V x MM JESD22-A115-A exceeds 200 V x CDM JESD22-C101-C exceeds 1000 V s Low static power consumption; ICC = 0.
9 µA (maximum) s Latch-up performance exceeds 100 mA per JESD 78 Class II s Inputs accept voltages up to 3.
6 V s Low noise overshoot and undershoot < 10 % of VCC s IOFF circuitry provides partial Power-down mode operation s Multiple package options s Specified from −40 °C to +85 °C and −40 °C to +125 °C Philips Semiconductors 74AUP1G02 Low-power 2-input NOR gate www.
DataSheet4U.
com 3.
Quick reference data Table 1: Quick reference data GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3 ns.
Symbol Parameter Conditions CL = 5 pF; RL = 1 MΩ; VCC = 0.
8 V CL = 5 pF; RL = 1 MΩ; VCC = 1.
1 V to 1.
3 V CL = 5 pF; RL = 1 MΩ; VCC = 1.
4 V to 1.
6 V CL = 5 pF; RL = 1 MΩ; VCC = 1.
65 V to 1.
95 V CL = 5 pF; RL = 1 MΩ; VCC = 2.
3 V to 2.
7 V CL = 5 pF; RL = 1 MΩ; VCC = 3.
0 V to 3.
6 V Ci CPD input capacitance power diss...


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