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MB91305

Fujitsu
Part Number MB91305
Manufacturer Fujitsu
Description 32-bit Microcontroller
Published Oct 15, 2010
Detailed Description www.DataSheet.in FUJITSU SEMICONDUCTOR DATA SHEET DS07-16703-1E 32-bit Microcontroller CMOS FR60 MB91305 MB91305 ■ D...
Datasheet PDF File MB91305 PDF File

MB91305
MB91305

Overview
www.
DataSheet.
in FUJITSU SEMICONDUCTOR DATA SHEET DS07-16703-1E 32-bit Microcontroller CMOS FR60 MB91305 MB91305 ■ DESCRIPTION MB91305 is a single-chip microcontroller that has a 32-bit high-performance RISC CPU as well as built-in I/O resources for embedded controllers requiring high-performance and high-speed CPU processing.
The FR family is the most suitable for embedded applications, for example, DVD player, printer, TV, and PDP control, that require a high level of CPU processing power.
MB91305 is an FR60 model that is based on the FR30/40 of CPUs.
It has enhanced bus access and is optimized for high-speed use.
■ FEATURES 1.
FR CPU • 32-bit RISC, load/store architecture, 5 stages pipeline • With USB function (MOD = 0000B) : operating frequency of 64 MHz [original oscillation at 48 MHz] 48 MHz / 3-divided × 4 multiplication (Continued) ■ PACKAGE 176-pin plastic LQFP (FPT-176P-M07) Copyright©2006 FUJITSU LIMITED All rights reserved www.
DataSheet.
in MB91305 (Continued) • With no USB function (MOD = 0010B) : operating frequency of 64 MHz [original oscillation at 16 MHz] 16 MHz × 4 multiplication • 16-bit fixed-length instructions (basic instructions) , one instruction per cycle • Memory-to-memory transfer, bit processing, instructions including barrel shift, etc.
: instructions appropriate for embedded applications • Function entry and exit instructions, multi load/store instructions of register contents : instructions compatible with high-level languages • Register interlock function to facilitate assembly-language coding • Built-in multiplier/instruction-level support - Signed 32-bit multiplication : 5 cycles - Signed 16-bit multiplication : 3 cycles • Interrupts (saving of PC and PS) : 6 cycles, 16 priority levels • Harvard architecture enabling simultaneous execution of both program access and data access • 4-word queues in the CPU provided to add an instruction prefetch function • Instructions compatible with the FR family 2.
Bus Interface This bus ...


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