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MB91307

Fujitsu Media Devices
Part Number MB91307
Manufacturer Fujitsu Media Devices
Description (MB91306R / MB91307R) 32-Bit Microcontroller
Published Oct 15, 2010
Detailed Description www.DataSheet4U.com FUJITSU SEMICONDUCTOR DATA SHEET DS07-16314-2E 32-Bit Microcontroller CMOS FR60 MB91307 Series ...
Datasheet PDF File MB91307 PDF File

MB91307
MB91307

Overview
www.
DataSheet4U.
com FUJITSU SEMICONDUCTOR DATA SHEET DS07-16314-2E 32-Bit Microcontroller CMOS FR60 MB91307 Series MB91306R/MB91307R ■ DESCRIPTION The FUJITSU FR family of single-chip microcontrollers using a 32-bit high-performance RISC CPU, with a variety of built-in I/O resources and bus control mechanisms for built-in control applications requiring high-capability, high-speed CPU processing.
External bus access is assumed in order to support the expanded address space accessible by the 32-bit CPU, and a 1K bytes cache memory plus large RAM are provided for high-speed execution of CPU instructions.
This microcontroller is ideal for built-in applications such as DVD players, navigation systems, high-capability FAX and printer control that demand high-capability CPU processing power.
The MB91307 series is a FR60 family product based on the FR30/40 family CPU with enhanced bus access for higher speed operation.
■ FEATURES FR CPU • 32-bit RISC, load/store architecture, 5-stage pipeline • Operating frequency 66MHz [with PLL: base frequency 16.
5 MHz] • 16-bit fixed length instructions (basic instructions), 1 instruction per cycle • Instructions for built-in applications: memory-to-memory transfer, bit processing, barrel shift etc.
• Instructions adapted for high-level languages: function input/output instructions, register contents multi-load/ store instructions (Continued) ■ PACKAGE 120-pin, plastic LQFP (FPT-120P-M21) DataSheet 4 U .
com www.
DataSheet4U.
com MB91307 Series • Easier assembler notation: register interlock function • Built-in multiplier/instruction level support Signed 32-bit multiplication: 5 cycles Signed 16-bit multiplication: 3 cycles • Interrupt (PC, PS removal): 6 cycles, 16 priority levels • Harvard architecture for simultaneous execution of program access and data access • CPU hold 4-word queue allows advanced instruction fetch function • 4G bytes expanded memory space enables linear access • Instruction compatible with FR30/40 family ...


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