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H27UAG8T2A

Hynix
Part Number H27UAG8T2A
Manufacturer Hynix
Description 16 Gbit (2048 M x 8 bit) NAND Flash
Published May 19, 2011
Detailed Description 1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash 16 Gb NAND Flash H27UAG8T2A www.DataSheet4U.net T...
Datasheet PDF File H27UAG8T2A PDF File

H27UAG8T2A
H27UAG8T2A

Overview
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash 16 Gb NAND Flash H27UAG8T2A www.
DataSheet4U.
net This document is a general product description and is subject to change without notice.
Hynix does not assume any responsibility for use of circuits described.
No patent licenses are implied.
Rev 0.
5 / Jul.
2009 1 1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash Document Title 16 Gbit (2048 M x 8 bit) NAND Flash Memory Revision History Revisio n No.
0.
0 0.
1 0.
2 Initial Draft.
Deleted ULGA PKG Changed 1.
ICC2 current: Typ 15mA/ Max 30mA => 20mA/40mA 2.
Added AC parameter values for cache operation 1.
Corrected Table 10 & Table 11.
5th byte of Device Identifier & Data 2.
Changed Figure 31 : Power on Reset 3.
Corrected Bad Block Management SLC to MLC Deleted supply voltage for I/O buffer (VCCQ) 1.
Corrected 5th cycle command from 34h to 44h at figure28.
Read ID operation.
2.
Changed tADL.
Min.
from 200 to 70 at Table 18:AC Timing Characteristics.
History Draft Date Jul.
16.
2008 Feb.
25.
2009 Mar.
30.
2009 Remark Preliminary Preliminary Preliminary 0.
3 0.
4 0.
5 Apr.
24.
2009 Apr.
29.
2009 Jul.
21.
2009 Preliminary Preliminary Preliminary www.
DataSheet4U.
net Rev 0.
5 / Jul.
2009 2 1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash FEATURES SUMMARY ELECTRONIC SIGNATURE HIGH DENSITY NAND FLASH MEMORIES - Cost effective solutions for mass storage applications - 1st cycle : Manufacturer Code - 2nd cycle : Device Code - 3rd cycle : Internal chip number, Cell Type, Number of Simultaneously Programmed Pages.
- 4th cycle : Page size, Block size, Organization, Spare size - 5th cycle : Multiplane Information - 6th cycle : Technology (Design Rule), EDO, Interface MULTIPLANE ARCHITECTURE - Array is split into two independent planes.
Parallel operations on both planes are available, halving program, read and erase time.
NAND INTERFACE - x8 bus width.
- Address / Data Multiplexing - Pin-out compatibility for all densit...


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