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L74VHC1GT08

Part Number	L74VHC1GT08
Manufacturer	LRC
Description	2-Input AND Gate
Published	Jun 20, 2011
Detailed Description	LESHAN RADIO COMPANY, LTD. 2-Input AND Gate with LSTTL–Compatible Inputs L74VHC1GT08 The L74VHC1G08 is an advanced hi...
Datasheet	L74VHC1GT08 PDF File

Overview

LESHAN RADIO COMPANY, LTD.
2-Input AND Gate with LSTTL–Compatible Inputs L74VHC1GT08 The L74VHC1G08 is an advanced high speed CMOS 2–input AND gate fabricated with silicon gate CMOS technology.
It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power issipation.
The internal circuit is composed of three stages, including an open drain output which provides the ability to set output switching level.
This allows the L74VHC1GT08 to be used to interface 5 V circuits to circuits of any voltage between V CC and 7 V using an external resistor and power supply.
The device input is compatible with TTL–type input thresholds and the output has a full 5.
0 V CMOS level output swing.
The input protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic–level translator from 3.
0 V CMOS logic to 5.
0 V CMOS Logic or from 1.
8 V CMOS logic to 3.
0 V CMOS Logic while operating at the high–voltage power supply.
The L74VHC1GT08 input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage.
This allows the L74VHC1GT08 to be used to interface 5 V circuits to 3 V circuits.
The output structures also provide protection when V CC = 0 V.
These input and output structures help prevent device destruction caused by supply voltage – input/output voltage mismatch, battery backup, hot insertion, etc.
• High Speed: t PD = 3.
5 ns (Typ) at V CC = 5 V • Low Power Dissipation: I CC = 2 mA (Max) at T A = 25°C • Power Down Protection Provided on Inputs • Balanced Propagation Delays • Pin and Function Compatible with Other Standard Logic Families • Chip Complexity: FETs = 62; Equivalent Gates = 15 MARKING DIAGRAMS 5 4 1 2 3 SC–88A / SOT–353/SC–70 DF SUFFIX V2d 5 4 Pin 1 d = Date Code Figure 1.
Pinout (Top View) 1 2 3 V2d Figure 2.
Logic Symbol Pin 1 d = Date Code TSOP–5/SOT–23/SC–59 DT SUFFIX FUNCTION TABLE PIN ASSIGNMENT 1 2 3 4 5 IN B IN A...

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