DatasheetsPDF.com

IDT72V3683

Integrated Device Technology
Part Number IDT72V3683
Manufacturer Integrated Device Technology
Description 3.3 VOLT CMOS SyncFIFO
Published Jun 26, 2011
Detailed Description 3.3 VOLT CMOS SyncFIFOTM WITH BUS-MATCHING 16,384 x 36 32,768 x 36 65,536 x 36 IDT72V3683 IDT72V3693 IDT72V36103 FEATU...
Datasheet PDF File IDT72V3683 PDF File

IDT72V3683
IDT72V3683


Overview
3.
3 VOLT CMOS SyncFIFOTM WITH BUS-MATCHING 16,384 x 36 32,768 x 36 65,536 x 36 IDT72V3683 IDT72V3693 IDT72V36103 FEATURES • • • • • • • Memory storage capacity: IDT72V3683 – 16,384 x 36 IDT72V3693 – 32,768 x 36 IDT72V36103 – 65,536 x 36 Clock frequencies up to 100 MHz (6.
5 ns access time) Clocked FIFO buffering data from Port A to Port B IDT Standard timing (using EF and FF) or First Word Fall Through Timing (using OR and IR flag functions) Programmable Almost-Empty and Almost-Full flags; each has five default offsets (8, 16, 64, 256 and 1,024) Serial or parallel programming of partial flags Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits (byte) • • • • • • • • • • Big- or Little-Endian format for word and byte bus sizes Retransmit Capability Reset clears data and configures FIFO, Partial Reset clears data but retains configuration settings Mailbox bypass registers for each FIFO Free-running CLKA and CLKB may be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) Easily expandable in width and depth Auto power down minimizes power dissipation Available in a space-saving 128-pin Thin Quad Flatpack (TQFP) Pin compatible with the lower density parts, IDT72V3623/ 72V3633/72V3643/72V3653/72V3663/72V3673 Industrial temperature range (–40°C to +85°C) is available FUNCTIONAL BLOCK DIAGRAM MBF1 Mail 1 Register Port-A Control Logic CLKA CSA W/RA ENA MBA RS1 RS2 PRS BusMatching Input Register Output Register FIFO1 Mail1, Mail2, Reset Logic 36 36 RAM ARRAY 36 16,384 x 36 32,768 x 36 65,536 x 36 36 RT RTM FIFO Retransmit Logic Write Pointer Read Pointer B0-B35 A0-A35 FF/IR AF Status Flag Logic EF/OR AE 36 36 FS2 FS0/SD FS1/SEN Programmable Flag Offset Registers 16 Timing Mode Port-B Control Logic Mail 2 Register MBF2 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
The SyncFIFO is a trademark of Integrated Device Technology, Inc.
FWFT CL...



Similar Datasheet


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)