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HY57V161610FTP-6I

Hynix Semiconductor
Part Number HY57V161610FTP-6I
Manufacturer Hynix Semiconductor
Description 16Mb Synchronous DRAM
Published Jul 12, 2014
Detailed Description 16Mb Synchronous DRAM based on 512K x 2Bank x16 I/O Document Title 2Bank x 512K x 16bits Synchronous DRAM Revision Hist...
Datasheet PDF File HY57V161610FTP-6I PDF File

HY57V161610FTP-6I
HY57V161610FTP-6I

Overview
16Mb Synchronous DRAM based on 512K x 2Bank x16 I/O Document Title 2Bank x 512K x 16bits Synchronous DRAM Revision History Revision No.
0.
1 1.
0 History Initial Draft Final Revision Draft Date Feb.
2006 Apr.
2006 Remark Preliminary www.
DataSheet4U.
com This document is a general product description and is subject to change without notice.
Hynix does not assume any responsibility for use of circuits described.
No patent licenses are implied.
Rev.
1.
0 / Apr.
2006 1 Synchronous DRAM Memory 16Mbit (1Mx16bit) HY57V161610FT(P)-xx(I) Series 11 DESCRIPTION THE Hynix HY57V161610F-Series is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the main memory and graphic applications which require large memory density and high bandwidth.
HY57V161610F-Series is organized as 2banks of 524,288x16.
HY57V161610F-Series is offering fully synchronous operation referenced to a positive edge clock.
All inputs and outputs are synchronized with the rising edge of the clock input.
The data paths are internally pipelined to achieve very high bandwidth.
All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 1,2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave).
A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle.
(This pipeline www.
DataSheet4U.
com design is not restricted by a '2N' rule.
) FEATURES • • • • • • Voltage: VDD, VDDQ 3.
3V supply voltage All device pins are compatible with LVTTL interface JEDEC standard 400mil 50pin TSOP-II with 0.
8mm of pin pitch (Lead or Lead Free Package) All inputs and outputs referenced to positive edge of system clock Data mask function by UDQM, LDQM Internal two banks operation • • • • • Auto refresh and self refr...


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