9DBL0843 Datasheet | 8-output 3.3V LP-HCSL Zero-Delay Buffer





(Datasheet) 9DBL0843 Datasheet PDF Download

Part Number 9DBL0843
Description 8-output 3.3V LP-HCSL Zero-Delay Buffer
Manufacture IDT
Total Page 19 Pages
PDF Download Download 9DBL0843 Datasheet PDF

Features: 8-output 3.3V LP-HCSL Zero-Delay Buffer with LOS Indicator 9DBL08x3 Datasheet General Description The 9DBL08x3 devic es are 3.3V members of IDT's Full-Featu red PCIe clock family. They support PCI e Gen1-4 Common Clock (CC) architecture s and also support NVLINK applications. The 9DBL08x3 parts have a Loss of Sign al (LOS) indicator to support fault-tol erant, high reliability systems. Recomm ended Application PCIe Gen1-4 and NVLIN K clock distribution for Riser Cards, S torage, Networking, JBOD, Communication s, Access Points Output Features ▪ Lo ss Of Signal (LOS) open drain output 8 – 1-200 MHz Low-Power (LP) HCSL D IF pairs ▪ 9DBL0843 default Zout = 10 0Ω ▪ 9DBL0853 default Zout = 85Ω ▪ Easy AC-coupling to other logic fam ilies, see IDT application note AN-891. Key Specifications ▪ PCIe Gen1-4 CC compliant in ZDB or fanout buffer mode ▪ Supports NVLINK at 156.25M in ZDB o r fanout buffer mode ▪ DIF cycle-to-c ycle jitter <50ps ▪ DIF output-to-output skew < 50ps ▪ Bypa.

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8-output 3.3V LP-HCSL Zero-Delay
Buffer with LOS Indicator
9DBL08x3
Datasheet
General Description
The 9DBL08x3 devices are 3.3V members of IDT's Full-Featured
PCIe clock family. They support PCIe Gen1-4 Common Clock (CC)
architectures and also support NVLINK applications. The 9DBL08x3
parts have a Loss of Signal (LOS) indicator to support fault-tolerant,
high reliability systems.
Recommended Application
PCIe Gen1-4 and NVLINK clock distribution for Riser Cards,
Storage, Networking, JBOD, Communications, Access Points
Output Features
Loss Of Signal (LOS) open drain output
8 – 1-200 MHz Low-Power (LP) HCSL DIF pairs
9DBL0843 default Zout = 100
9DBL0853 default Zout = 85
Easy AC-coupling to other logic families, see IDT application note
AN-891.
Key Specifications
PCIe Gen1-4 CC compliant in ZDB or fanout buffer mode
Supports NVLINK at 156.25M in ZDB or fanout buffer mode
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew < 50ps
Bypass mode additive phase jitter is 0 ps typical rms for PCIe
Bypass mode additive phase jitter 160fs rms typ. @ 156.25M
(1.5M to 10M)
Block Diagram
vOE(7:0)#
7
Features/Benefits
LOS indicator signals loss of input clock; adds fault tolerance,
eases system diagnostics
Direct connection to 100(xx43) or 85(xx53) transmission
lines; saves 32 resistors compared to standard PCIe devices
205mW typical power consumption (PLL mode@3.3V); eliminates
thermal concerns
VDDIO allows >33% power savings at optional 1.05V; maximum
power savings
OE# pin for each DIF output; support DIF power management
HCSL-compatible differential input; can be driven by common
clock sources
Spread Spectrum tolerant; allows reduction of EMI
Outputs blocked until PLL is locked; clean system start-up
Pin/SMBus selectable PLL bandwidth and PLL Bypass; minimize
phase jitter for each application
Device contains default configuration; SMBus interface not
required for device operation
3 selectable SMBus addresses; multiple devices can easily share
an SMBus segment
SMBus-selectable features allows optimization to customer
requirements:
control input polarity
control input pull up/downs
slew rate for each output
differential output amplitude
output impedance for each output
Contact IDT for quick-turn customization of SMBus defaults;
allows exact optimization to customer requirements
Space saving 48-pin 6 × 6mm VFQFPN; minimal board space
CLK_IN
CLK_IN#
vSAD R_ tri
^vH IBW_ BYPM_ L OBW #
^C KPW RGD_ PD#
SDATA_3.3
SCLK_3.3
SS
C o mpa tib le
PLL
LOS
Logic
D IF7
8 Outputs
D IF0
L OS
©2017 Integrated Device Technology, Inc
1
February 1, 2017

                    
                    






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