5P49V5914 Generator Datasheet

5P49V5914 Datasheet, PDF, Equivalent


Part Number

5P49V5914

Description

Programmable Clock Generator

Manufacture

Renesas

Total Page 30 Pages
Datasheet
Download 5P49V5914 Datasheet


5P49V5914
Programmable Clock Generator
5P49V5914
DATASHEET
Description
Features
The 5P49V5914 is a programmable clock generator intended
for high performance consumer, networking, industrial,
computing, and data-communications applications.
Configurations may be stored in on-chip One-Time
Programmable (OTP) memory or changed using I2C
interface. This is IDTs fifth generation of programmable clock
technology (VersaClock® 5).
The frequencies are generated from a single reference clock.
The reference clock can come from one of the two redundant
clock inputs. A glitchless manual switchover function allows
one of the redundant clocks to be selected during normal
operation.
Two select pins allow up to 4 different configurations to be
programmed and accessible using processor GPIOs or
bootstrapping. The different selections may be used for
different operating modes (full function, partial function, partial
power-down), regional standards (US, Japan, Europe) or
system production margin testing.
The device may be configured to use one of two I2C
addresses to allow multiple devices to be used in a system.
Pin Assignment
CLKIN
CLKINB
XOUT
XIN/REF
VDDA
CLKSEL
1 24 23
22
21
20
19
18
2 17
3
EPAD
16
4
GND
15
5 14
6 13
7 8 9 10 11 12
VDDO2
OUT2
OUT2B
VDDO3
OUT3
OUT3B
24-pin VFQFPN
Generates up to three independent output frequencies
High performance, low phase noise PLL, <0.7ps RMS
typical phase jitter on outputs:
– PCIe Gen1, 2, 3 compliant clock capability
– USB 3.0 compliant clock capability
– 1GbE and 10GbE
Three fractional output dividers (FODs)
Independent Spread Spectrum capability on each output
pair
Four banks of internal non-volatile in-system
programmable or factory programmable OTP memory
I2C serial programming interface
One reference LVCMOS output clock
Three universal output pairs:
– Each configurable as one differential output pair or two
LVCMOS outputs
I/O Standards:
– Single-ended I/Os: 1.8V to 3.3V LVCMOS
– Differential I/Os: LVPECL, LVDS and HCSL
Input frequency ranges:
– LVCMOS Reference Clock Input (XIN/REF) – 1MHz to
200MHz
– LVDS, LVPECL, HCSL Differential Clock Input (CLKIN,
CLKINB) – 1MHz to 350MHz
– Crystal frequency range: 8MHz to 40MHz
Output frequency ranges:
– LVCMOS Clock Outputs – 1MHz to 200MHz
– LVDS, LVPECL, HCSL Differential Clock Outputs –
1MHz to 350MHz
Individually selectable output voltage (1.8V, 2.5V, 3.3V) for
each output pair
Redundant clock inputs with manual switchover
Programmable loop bandwidth
Programmable slew rate control
Programmable crystal load capacitance
Individual output enable/disable
Power-down mode
1.8V, 2.5V or 3.3V core VDDD, VDDA
Available in 24-pin VFQFPN 4mm x 4mm package
-40° to +85°C industrial temperature operation
5P49V5914 SEPTEMBER 12, 2018 1 ©2018 Integrated Device Technology, Inc.

5P49V5914
5P49V5914 DATASHEET
Functional Block Diagram
XIN/REF
XOUT
CLKIN
CLKINB
CLKSEL
SD/OE
SEL1/SDA
SEL0/SCL
VDDA
VDDD
OTP
and
Control Logic
Applications
Ethernet switch/router
PCI Express 1.0/2.0/3.0
Broadcast video/audio timing
Multi-function printer
Processor and FPGA clocking
Any-frequency clock conversion
MSAN/DSLAM/PON
Fiber Channel, SAN
Telecom line cards
1 GbE and 10 GbE
PLL
FOD1
FOD2
FOD3
PROGRAMMABLE CLOCK GENERATOR
2
VDDO0
OUT0_SEL_I2CB
VDDO1
OUT1
OUT1B
VDDO2
OUT2
OUT2B
VDDO3
OUT3
OUT3B
SEPTEMBER 12, 2018


Features Programmable Clock Generator 5P49V5914 DATASHEET Description Features The 5P49V5914 is a programmable clock gener ator intended for high performance cons umer, networking, industrial, computing , and data-communications applications. Configurations may be stored in on-chi p One-Time Programmable (OTP) memory or changed using I2C interface. This is I DTs fifth generation of programmable cl ock technology (VersaClock® 5). The fr equencies are generated from a single r eference clock. The reference clock can come from one of the two redundant clo ck inputs. A glitchless manual switchov er function allows one of the redundant clocks to be selected during normal op eration. Two select pins allow up to 4 different configurations to be programm ed and accessible using processor GPIOs or bootstrapping. The different select ions may be used for different operatin g modes (full function, partial functio n, partial power-down), regional standa rds (US, Japan, Europe) or system production margin testing. The.
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