SEMD48
NPN/PNP Silicon Digital Transistor Array
Preliminary data
• Switching circuit, inverter, interface circuit,
driver circuit
• Two (galvanic) internal isolated NPN/PNP
Transistors in one package
• Built in bias resistor
NPN: R1 = 47kΩ, R2 = 47kΩ
PNP: R1= 2.2kΩ, R2 = 47kΩ
4
5
6
3
2
1
Tape loading orientation
Top View
3 21
45 6
Direction of Unreeling
Marking on SOT666 package
(for example W R)
corresponds to pin 1 of device
Position in tape: pin 1
same of feed hole
side
C1 B2 E2
654
R2
R1
TR1 R1
R2
TR2
123
E1 B1 C2
EHA07176
Type
SEMD48
Marking
WT
Pin Configuration
Package
1=E1 2=B1 3=C2 4=E2 5=B2 6=C1 SOT666
Maximum Ratings
Parameter
Collector-emitter voltage
Collector-base voltage
Emitter-base voltage
NPN
Emitter-base voltage
PNP
Input on voltage
NPN
Input on voltage
PNP
DC collector current
NPN
DC collector current
PNP
Total power dissipation, TS = 75 °C
Junction temperature
Storage temperature
Symbol
VCEO
VCBO
VEBO
VEBO
Vi(on)
Vi(on)
IC
IC
Ptot
Tj
Tstg
Value
50
50
10
5
50
10
70
100
250
150
-65...+150
Unit
V
mA
mW
°C
1 Feb-26-2004
