ATR0635 Supersense Datasheet

ATR0635 Datasheet, PDF, Equivalent


Part Number

ATR0635

Description

Single-Chip GPS Receiver Supersense

Manufacture

ATMEL Corporation

Total Page 30 Pages
Datasheet
Download ATR0635 Datasheet


ATR0635
www.DataSheet4U.com
Features
16-channel GPS Correlator
– 8192 Search Bins with GPS Acquisition Accelerator
– Accuracy: 2.5m CEP (2D, Stand Alone)
– Time to First Fix: 34s (Cold Start)
– Acquisition Sensitivity: –142 dBm (With External LNA)
– Tracking Sensitivity: –158 dBm (With External LNA)
Utilizes the ARM7TDMI® ARM® Thumb® Processor Core
– High-performance 32-bit RISC Architecture
– Embedded ICE (In-Circuit Emulation)
128 Kbytes Internal RAM
384 Kbytes Internal ROM with u-blox GPS Firmware SuperSense
1.5-bit ADC On-chip
Single IF Architecture
2 External Interrupts
24 User-programmable I/O Lines
1 USB Device Port
– Universal Serial Bus (USB) 2.0 Full-speed Device
– Embedded USB V2.0 Full-speed Transceiver
2 USARTs
Master/Slave SPI Interface
– 4 External Slave Chip Selects
Programmable Watchdog Timer
Advanced Power Management Controller (APMC)
– Geared Master Clock to Reduce Power Consumption
– Sleep State with Disabled Master Clock
– Hibernate State with 32.768 kHz Master Clock
Real Time Clock (RTC)
1.8V to 3.3V User-definable IO Voltage for Several GPIOs with 5V Tolerance
4 KBytes of Battery Backup Memory
7 mm × 10 mm 96 Pin BGA Package, 0.8 mm Pitch, Pb-free, RoHS-compliant
Benefits
Fully Integrated Design With Low BOM
No External Flash Memory Required
Supports NMEA, UBX Binary and RTCM Protocol
Supports SBAS (WAAS, EGNOS, MSAS)
Up to 4Hz Update Rate
Supports A-GPS (Aiding)
Excellent Noise Performance
ANTARIS4
Single-chip
GPS Receiver
SuperSense
ATR0635
Preliminary
4928B–GPS–04/06

ATR0635
www.DataSheet4U.com
1. Description
The ATR0635 is a low-power, single-chip GPS receiver, especially designed to meet the
requirements of mobile applications. It is based on Atmel’s ANTARIS4 technology and inte-
grates an RF front-end, filtering, and a baseband processor in a single, tiny 7 mm × 10 mm
96 pin BGA package. Providing excellent RF performance with low noise figure and low power
consumption.
Due to the fully integrated design, just an RF SAW filter, a GPS TCXO and blocking capacitors
are required to realize a stand-alone GPS functionality.
The ATR0635 includes a complete GPS firmware, licensed from u-blox AG, which performs the
GPS operation, including tracking, acquisition, navigation and position data output. For normal
PVT (Position/Velocity/Time) applications, there is no need for external Flash- or ROM-memory.
The firmware supports the possibility to store the configuration settings in an optional external
EEPROM.
Due to the integrated ARM7TDMI processor and an intelligent radio architecture, the ATR0635
operates in a complete autonomous mode, utilizing on chip AGC in closed loop operation.
For maximum performance, we recommend to use the ATR0635 together with a low noise
amplifier (e.g. ATR0610).
The ATR0635 supports assisted GPS.
2 ATR0635 [Preliminary]
4928B–GPS–04/06


Features www.DataSheet4U.com Features • 16-cha nnel GPS Correlator – 8192 Search Bin s with GPS Acquisition Accelerator – Accuracy: 2.5m CEP (2D, Stand Alone) Time to First Fix: 34s (Cold Start) Acquisition Sensitivity: –142 dBm (With External LNA) – Tracking Sensit ivity: –158 dBm (With External LNA) U tilizes the ARM7TDMI® ARM® Thumb® Pr ocessor Core – High-performance 32-bi t RISC Architecture – Embedded ICE (I n-Circuit Emulation) 128 Kbytes Interna l RAM 384 Kbytes Internal ROM with u-bl ox GPS Firmware SuperSense™ 1.5-bit A DC On-chip Single IF Architecture 2 Ext ernal Interrupts 24 User-programmable I /O Lines 1 USB Device Port – Universa l Serial Bus (USB) 2.0 Full-speed Devic e – Embedded USB V2.0 Full-speed Tran sceiver 2 USARTs Master/Slave SPI Inter face – 4 External Slave Chip Selects Programmable Watchdog Timer Advanced Po wer Management Controller (APMC) – Ge ared Master Clock to Reduce Power Consu mption – Sleep State with Disabled Master Clock – Hibernate State with 32.768 kHz Master Clock R.
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