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NAND gate. 74AUP1G00 Datasheet

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NAND gate. 74AUP1G00 Datasheet






74AUP1G00 gate. Datasheet pdf. Equivalent




74AUP1G00 gate. Datasheet pdf. Equivalent





Part

74AUP1G00

Description

Low-power 2-input NAND gate



Feature


www.DataSheet4U.com 74AUP1G00 Low-power 2-input NAND gate Rev. 02 — 29 June 2006 Product data sheet 1. General des cription The 74AUP1G00 is a high-perfor mance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt-t rigger action at all inputs makes the c ircuit tolerant to slower input rise an d fall times across .
Manufacture

NXP Semiconductors

Datasheet
Download 74AUP1G00 Datasheet


NXP Semiconductors 74AUP1G00

74AUP1G00; the entire VCC range from 0.8 V to 3.6 V . This device ensures a very low static and dynamic power consumption across t he entire VCC range from 0.8 V to 3.6 V . This device is fully specified for p artial Power-down applications using IO FF. The IOFF circuitry disables the out put, preventing the damaging backflow current through the device when it is p owered down. The 74AUP.


NXP Semiconductors 74AUP1G00

1G00 provides the single 2-input NAND fu nction. 2. Features s Wide supply volt age range from 0.8 V to 3.6 V s High no ise immunity s Complies with JEDEC stan dards: x JESD8-12 (0.8 V to 1.3 V) x JE SD8-11 (0.9 V to 1.65 V) x JESD8-7 (1.2 V to 1.95 V) x JESD8-5 (1.8 V to 2.7 V ) x JESD8-B (2.7 V to 3.6 V) s ESD prot ection: x HBM JESD22-A114-C Class 3A. E xceeds 5000 V x MM.


NXP Semiconductors 74AUP1G00

JESD22-A115-A exceeds 200 V x CDM JESD2 2-C101-C exceeds 1000 V s Low static po wer consumption; ICC = 0.9 µA (maximum ) s Latch-up performance exceeds 100 mA per JESD 78 Class II s Inputs accept v oltages up to 3.6 V s Low noise oversho ot and undershoot < 10 % of VCC s IOFF circuitry provides partial Power-down m ode operation s Multiple package option s s Specified from −.

Part

74AUP1G00

Description

Low-power 2-input NAND gate



Feature


www.DataSheet4U.com 74AUP1G00 Low-power 2-input NAND gate Rev. 02 — 29 June 2006 Product data sheet 1. General des cription The 74AUP1G00 is a high-perfor mance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt-t rigger action at all inputs makes the c ircuit tolerant to slower input rise an d fall times across .
Manufacture

NXP Semiconductors

Datasheet
Download 74AUP1G00 Datasheet




 74AUP1G00
www.DataSheet4U.com
74AUP1G00
Low-power 2-input NAND gate
Rev. 02 — 29 June 2006
Product data sheet
1. General description
The 74AUP1G00 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74AUP1G00 provides the single 2-input NAND function.
2. Features
s Wide supply voltage range from 0.8 V to 3.6 V
s High noise immunity
s Complies with JEDEC standards:
x JESD8-12 (0.8 V to 1.3 V)
x JESD8-11 (0.9 V to 1.65 V)
x JESD8-7 (1.2 V to 1.95 V)
x JESD8-5 (1.8 V to 2.7 V)
x JESD8-B (2.7 V to 3.6 V)
s ESD protection:
x HBM JESD22-A114-C Class 3A. Exceeds 5000 V
x MM JESD22-A115-A exceeds 200 V
x CDM JESD22-C101-C exceeds 1000 V
s Low static power consumption; ICC = 0.9 µA (maximum)
s Latch-up performance exceeds 100 mA per JESD 78 Class II
s Inputs accept voltages up to 3.6 V
s Low noise overshoot and undershoot < 10 % of VCC
s IOFF circuitry provides partial Power-down mode operation
s Multiple package options
s Specified from 40 °C to +85 °C and 40 °C to +125 °C




 74AUP1G00
www.DPahtaSilhiepest4US.ceommiconductors
74AUP1G00
Low-power 2-input NAND gate
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74AUP1G00GW 40 °C to +125 °C TSSOP5
74AUP1G00GM 40 °C to +125 °C XSON6
74AUP1G00GF 40 °C to +125 °C XSON6
Description
Version
plastic thin shrink small outline package; 5 leads;
body width 1.25 mm
SOT353-1
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1 × 1.45 × 0.5 mm
plastic extremely thin small outline package; no leads; SOT891
6 terminals; body 1 × 1 × 0.5 mm
4. Marking
Table 2. Marking
Type number
74AUP1G00GW
74AUP1G00GM
74AUP1G00GF
5. Functional diagram
Marking code
pA
pA
pA
1B
2A
Y4
mna097
Fig 1. Logic symbol
1
&4
2
mna098
Fig 2. IEC logic symbol
6. Pinning information
6.1 Pinning
B
A
Fig 3. Logic diagram
Y
mna099
74AUP1G00
B1
5 VCC
A2
GND 3
4Y
001aaf016
Fig 4. Pin configuration SOT353-1
(TSSOP5)
74AUP1G00_2
Product data sheet
74AUP1G00
B1
6 VCC
A2
5 n.c.
GND 3
4Y
001aaf017
Transparent top view
Fig 5. Pin configuration SOT886
(XSON6)
Rev. 02 — 29 June 2006
74AUP1G00
B1
A2
6 VCC
5 n.c.
GND 3
4Y
001aaf018
Transparent top view
Fig 6. Pin configuration SOT891
(XSON6)
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
2 of 16




 74AUP1G00
www.DPahtaSilhiepest4US.ceommiconductors
74AUP1G00
Low-power 2-input NAND gate
6.2 Pin description
Table 3.
Symbol
B
A
GND
Y
n.c.
VCC
Pin description
Pin
TSSOP5
1
2
3
4
-
5
XSON6
1
2
3
4
5
6
7. Functional description
Description
data input B
data input A
ground (0 V)
data output Y
not connected
supply voltage
Table 4.
Input
A
L
L
H
H
Function table[1]
[1] H = HIGH voltage level;
L = LOW voltage level.
8. Limiting values
B
L
H
L
H
Output
Y
H
H
H
L
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min Max Unit
VCC supply voltage
IIK
input clamping current
VI < 0 V
VI input voltage
IOK output clamping current VO > VCC or VO < 0 V
VO output voltage
Active mode
Power-down mode
0.5
-
[1] 0.5
-
[1] 0.5
[1] 0.5
+4.6
50
+4.6
±50
VCC + 0.5
+4.6
V
mA
V
mA
V
V
IO output current
VO = 0 V to VCC
- ±20 mA
ICC
IGND
Tstg
Ptot
supply current
ground current
storage temperature
total power dissipation
Tamb = 40 °C to +125 °C
-
-
65
[2] -
+50
50
+150
250
mA
mA
°C
mW
[1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For TSSOP5 packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K.
74AUP1G00_2
Product data sheet
Rev. 02 — 29 June 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
3 of 16



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