5P49V5923 Clock Generator Datasheet

5P49V5923 Datasheet, PDF, Equivalent


Part Number

5P49V5923

Description

Programmable Clock Generator

Manufacture

Integrated Device Technology

Total Page 27 Pages
Datasheet
Download 5P49V5923 Datasheet


5P49V5923
Programmable Clock Generator
5P49V5923
DATASHEET
Description
The 5P49V5923 is a programmable clock generator intended
for high performance consumer, networking, industrial,
computing, and data-communications applications.
Configurations may be stored in on-chip One-Time
Programmable (OTP) memory or changed using I2C
interface. This is IDT’s fifth generation of programmable clock
technology (VersaClock® 5).
The frequencies are generated from a single reference clock.
The reference clock can come from one of the two redundant
clock inputs. A glitchless manual switchover function allows
one of the redundant clocks to be selected during normal
operation.
Two select pins allow up to 4 different configurations to be
programmed and accessible using processor GPIOs or
bootstrapping. The different selections may be used for
different operating modes (full function, partial function, partial
power-down), regional standards (US, Japan, Europe) or
system production margin testing.
The device may be configured to use one of two I2C
addresses to allow multiple devices to be used in a system.
Pin Assignment
CLKIN
CLKINB
XOUT
XIN/REF
VDDA
CLKSEL
1 24 23
22
21
20
19
18
2 17
3
EPAD
16
4
GND
15
5 14
6 13
7 8 9 10 11 12
VDDO2
OUT2
NC
VDDA
NC
NC
Features
Generates up to two independent output frequencies
High performance, low phase noise PLL, <0.7 ps RMS
typical phase jitter on outputs
Two fractional output dividers (FODs)
Independent Spread Spectrum capability on each output
Four banks of internal non-volatile in-system
programmable or factory programmable OTP memory
I2C serial programming interface
Three LVCMOS outputs, including one reference output
I/O Standards:
– Single-ended I/Os: 1.8V to 3.3V LVCMOS
Input frequency ranges:
– LVCMOS Reference Clock Input (XIN/REF) – 1MHz to
200MHz
– LVDS, LVPECL, HCSL Differential Clock Input (CLKIN,
CLKINB) – 1MHz to 200MHz
– Crystal frequency range: 8MHz to 40MHz
Output frequency ranges:
– LVCMOS Clock Outputs – 1MHz to 200MHz
Individually selectable output voltage (1.8V, 2.5V, 3.3V) for
each output
Redundant clock inputs with manual switchover
Programmable loop bandwidth
Programmable slew rate control
Programmable crystal load capacitance
Individual output enable/disable
Power-down mode
1.8V, 2.5V or 3.3V core VDDD, VDDA
Available in 24-pin VFQFPN 4mm x 4mm package
-40° to +85°C industrial temperature operation
24-pin VFQFPN
5P49V5923 FEBRUARY 21, 2019
1
©2019 Integrated Device Technology, Inc.

5P49V5923
5P49V5923 DATASHEET
Functional Block Diagram
XIN/REF
XOUT
CLKIN
CLKINB
CLKSEL
SD/OE
SEL1/SDA
SEL0/SCL
VDDA
VDDD
OTP
and
Control Logic
Applications
Ethernet switch/router
PCI Express 1.0/2.0/3.0
Broadcast video/audio timing
Multi-function printer
Processor and FPGA clocking
Any-frequency clock conversion
MSAN/DSLAM/PON
Fiber Channel, SAN
Telecom line cards
1 GbE and 10 GbE
PLL
FOD1
FOD2
PROGRAMMABLE CLOCK GENERATOR
2
VDDO0
OUT0_SEL_I2CB
VDDO1
OUT1
VDDO2
OUT2
VDDA
VDDA
FEBRUARY 21, 2019


Features Programmable Clock Generator 5P49V5923 DATASHEET Description The 5P49V5923 i s a programmable clock generator intend ed for high performance consumer, netwo rking, industrial, computing, and data- communications applications. Configurat ions may be stored in on-chip One-Time Programmable (OTP) memory or changed us ing I2C interface. This is IDT’s fift h generation of programmable clock tech nology (VersaClock® 5). The frequencie s are generated from a single reference clock. The reference clock can come fr om one of the two redundant clock input s. A glitchless manual switchover funct ion allows one of the redundant clocks to be selected during normal operation. Two select pins allow up to 4 differen t configurations to be programmed and a ccessible using processor GPIOs or boot strapping. The different selections may be used for different operating modes (full function, partial function, parti al power-down), regional standards (US, Japan, Europe) or system production margin testing. The device.
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