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SAA7219

NXP
Part Number SAA7219
Manufacturer NXP
Description MPEG2 Transport RISC processor
Published Apr 8, 2005
Detailed Description INTEGRATED CIRCUITS DATA SHEET SAA7219 MPEG2 Transport RISC processor Preliminary specification File under Integrated C...
Datasheet PDF File SAA7219 PDF File

SAA7219
SAA7219

Overview
INTEGRATED CIRCUITS DATA SHEET SAA7219 MPEG2 Transport RISC processor Preliminary specification File under Integrated Circuits, IC02 1999 Sep 20 Philips Semiconductors Preliminary specification MPEG2 Transport RISC processor CONTENTS 1 1.
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5 9 10 11 FEATURES External interfaces CPU related features MPEG-2 systems features GENERAL DESCRIPTION SAA7219 overview SAA7219 in a DVB system ORDERING INFORMATION BLOCK DIAGRAM PINNING INFORMATION Pinning Pin description APPLICATION INFORMATION Memory configurations PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS SAA7219 1999 Sep 20 2 Philips Semiconductors Preliminary specification MPEG2 Transport RISC processor 1 FEATURES SAA7219 • Conditional access descrambling Digital Video Broadcasting (DVB) compliant and MULTI2 compliant • Stream demultiplexing: Transport Stream (TS), Packetized Elementary Stream (PES), program and proprietary streams • Internal 32-bit MIPS RISC based Central Processing Unit (CPU) supporting MIPS16 instruction set and running at 81 MHz • Low-power sleep modes supported across the chip • Comprehensive driver software and development tool support • Package: SQFP208.
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1 External interfaces • A General Purpose/High Speed (GP/HS) interface supporting stream recording through IEEE 1394 interface IC • An extended JTAG interface for board test support.
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2 CPU related features The SAA7219 contains an embedded RISC CPU, which incorporates the following features: • A 32-bit PR3930 core running at 81 MHz • 8-kbyte, 2-way set associative instruction cache • 4-kbyte, 4-way set associative data cache • A programmable Low-power mode, including wake-up on interrupt • A memory management unit with 32 odd/even entries and vari...


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