4 Banks x 1M x 32Bit Synchronous DRAM
Description
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HY57V283220(L)T(P)/ HY5V22(L)F(P)
4 Banks x 1M x 32Bit Synchronous DRAM
Revision History
Revision No. 0.1 History Defined Preliminary Specification 1) 2) 3) 4) 5) 6) Modified FBGA Ball Configuration Typo. Changed Functional Block Diagram from A10 to A11. Changed VDD min from 3.0V to 3.135V. Changed Cap. Value from C11, 3, 5 to 4pf & C12...
Hynix Semiconductor
HY5V22F PDF File
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