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Part Number
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MK2049-36 |
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Manufacturer
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Integrated Circuit Systems |
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Description
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3.3 V Communications Clock PLL |
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Published
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May 7, 2005 |
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Detailed Description
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PRELIMINARY INFORMATION
MK2049-36 3.3 V Communications Clock PLL
Features
• Packaged in 20 pin SOIC • 3.3 V ±5% operati...
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Datasheet
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MK2049-36
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Overview
PRELIMINARY INFORMATION
MK2049-36 3.
3 V Communications Clock PLL
Features
• Packaged in 20 pin SOIC • 3.
3 V ±5% operation • Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E • Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50 MHz • Locks to 8 kHz ±100 ppm (External mode) • Buffer Mode allows jitter attenuation of 10-50 MHz input and x1/x0.
5 or x1/x2 outputs • Exact internal ratios enable zero ppm error • Output clock rates include T1, E1, T3, E3, and OC3 submultiples • See the MK2049-01, -02, and -03 for more selections at VDD = 5 V, and the MK2049-34 for more selections at 3.
3...
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