LH540203 FEATURES • Fast Access Times: 15/20/25/35/50 ns • Fast-Fall-Through Time Architecture Based on CMOS Dual-Port SRAM Technology • Input Port and Output Port Have Entirely Independent Timing • Expandable in Width and Depth • Full, Half-Full, and Empty Status Flags • Data Retransmission Capability • TTL-Compatible I/O • Pin and Functionally Compatible with Sharp LH5498 and with Am/IDT/MS7203 • Control Signals Assertive-LOW for Noise Immunity • Packages: 28-Pin, 300-mil PDIP 28-Pin, 300-mil SOJ * 32-Pin PLCC CMOS 2048 × 9 Asynchronous FIFO FUNCTIONAL DESCRIPTION The LH540203 is a FIFO (First-In, First-Out) memory device, based on fully-static CMOS dual-port SRAM technology, capable of s...

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