LH540205 FEATURES • Fast Access Times: 20/25/35/50 ns • Fast-Fall-Through Time Architecture Based on CMOS Dual-Port SRAM Technology • Input Port and Output Port Have Entirely Independent Timing • Expandable in Width and Depth • Full, Half-Full, and Empty Status Flags • Data Retransmission Capability • TTL-Compatible I/O • Pin and Functionally Compatible with Am/IDT7205 • Control Signals Assertive-LOW for Noise Immunity • Package: 28-Pin, 300-mil PDIP CMOS 8192 × 9 Asynchronous FIFO Data words are read out from the LH540205’s output port in precisely the same order that they were written in at its input port; that is, according to a First-In, First Out (FIFO) queue discipline.
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