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DS3100

Microsemi
Part Number DS3100
Manufacturer Microsemi
Description Stratum 2/3E/3 Timing Card-IC
Published Aug 28, 2016
Detailed Description Data Sheet April 2019 DS3100 Stratum 2/3E/3 Timing Card IC General Description When paired with an external TCXO or OC...
Datasheet PDF File DS3100 PDF File

DS3100
DS3100

Overview
Data Sheet April 2019 DS3100 Stratum 2/3E/3 Timing Card IC General Description When paired with an external TCXO or OCXO, the DS3100 is a complete central timing and synchronization solution for SONET/SDH network elements.
With two multiprotocol BITS/SSU receivers and 14 input clocks, the device directly accepts both external timing and line timing from a large number of line cards.
All input clocks are continuously monitored for frequency accuracy and activity.
Any two of the input clocks can be selected as the references for the two core DPLLs.
The T0 DPLL complies with the Stratum 2, 3E, 3, 4E and 4 requirements of GR1244, GR-253, G.
812 Types I – IV, G.
813 and G.
8262.
From the output of the core DPLLs, a wide variety of output clock frequencies and frame pulses can be produced simultaneously on the 11 output clock pins.
Two DS3100 devices can be configured in a master/slave arrangement for timing card equipment protection.
The DS3100 registers and I/O pins are backward compatible with Semtech’s ACS8520 and ACS8530 timing card ICs.
Applications SONET/SDH ADMs, MSPPs, and MSSPs Digital Cross-Connects DSLAMs Service Provider Routers Functional Diagram TIMING FROM LINE CARDS (VARIOUS RATES) 14 TIMING FROM BITS/SSU (DS1, E1, CC, ETC.
) 2 LOCAL TCXO OR OCXO DS3100 2 SONET/SDH Synchronization IC 11 TIMING TO BITS/SSU (DS1, E1, CC, ETC.
) TIMING TO LINE CARDS (VARIOUS RATES) CONTROL STATUS Features ▪ Synchronization Subsystem for Stratum 2, 3E, 3, 4E and 4 plus SMC, SEC and EEC - Meets Requirements of GR-1244 Stratum 2 - 4, GR-253, G.
812 Types I - IV, G.
813 and G.
8262 - Stratum 2, 3E or 3 Holdover Accuracy with Suitable External Oscillator - Programmable Bandwidth, 0.
5mHz to 70Hz - Hitless Reference Switching on Loss of Input - Phase Build-Out and Transient Absorption - Locks to and Generates 125MHz for Gigabit Synchronous Ethernet per ITU-T G.
8261 ▪ 14 Input Clocks - 10 CMOS/TTL Inputs Accept 2kHz, 4kHz, and Any Multiple of 8kHz Up to 125MHz - Two LVDS/LVPECL/CMOS...


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