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DS92LV3241

Texas Instruments
Part Number DS92LV3241
Manufacturer Texas Instruments
Description Link-II Serializer/Deserializer
Published Dec 25, 2020
Detailed Description DS92LV3241, DS92LV3242 www.ti.com SNLS314D – SEPTEMBER 2009 – REVISED APRIL 2013 DS92LV3241/DS92LV3242 20-85 MHz 32-B...
Datasheet PDF File DS92LV3241 PDF File

DS92LV3241
DS92LV3241

Overview
DS92LV3241, DS92LV3242 www.
ti.
com SNLS314D – SEPTEMBER 2009 – REVISED APRIL 2013 DS92LV3241/DS92LV3242 20-85 MHz 32-Bit Channel Link II Serializer / Deserializer Check for Samples: DS92LV3241, DS92LV3242 FEATURES 1 •2 Wide Operating Range Embedded Clock SER/DES – Up to 32-bit Parallel LVCMOS Data – 20 to 85 MHz Parallel Clock – Up to 2.
72 Gbps Application Data Paylod • Selectable Serial LVDS Bus Width – Dual Lane Mode (20 to 50 MHz) – Quad Lane Mode (40 to 85 MHz) • Simplified Clocking Architecture – No Separate Serial Clock Line – No reference Clock Required – Receiver Locks to Random Data • On-Chip Signal Conditioning for Robust Serial Connectivity – Transmit Pre-Emphasis – Data Randomization – DC-Balance Encoding – Receive Channel Deskew – Supports up to 10m CAT-5 at 2.
7 Gbps • Integrated LVDS Terminations • Built-in AT-SPEED BIST for End-to-End System Testing • AC-Coupled Interconnect for Isolation and Fault Protection • > 4KV HBM ESD Protection • Space-Saving 64-pin TQFP Package • Full Industrial Temperature Range : -40° to +85°C APPLICATIONS • Industrial Imaging (Machine-Vision) and Control • Security & Surveillance Cameras and Infrastructure • Medical imaging • Up to 30 bits per Pixel, VGA to HD Video Transport and Display DESCRIPTION The DS92LV3241 (SER) serializes a 32-bit data bus into 2 or 4 (selectable) embedded clock LVDS serial channels for a data payload rate up to 2.
72 Gbps over cables such as CATx, or backplanes FR-4 traces.
The companion DS92LV3242 (DES) deserializes the 2 or 4 LVDS serial data channels, de-skews channel-to-channel delay variations and converts the LVDS data stream back into a 32-bit LVCMOS parallel data bus.
On-chip data Randomization/Scrambling and DC balance encoding and selectable serializer Preemphasis ensure a robust, low-EMI transmission over longer, lossy cables and backplanes.
The Deserializer automatically locks to incoming data without an external reference clock or special sync patterns, providing an easy “plug-and...


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