DatasheetsPDF.com

DS92LV3222

Texas Instruments
Part Number DS92LV3222
Manufacturer Texas Instruments
Description Link-II Serializer/Deserializer
Published Dec 25, 2020
Detailed Description DS92LV3221, DS92LV3222 www.ti.com SNLS319C – OCTOBER 2009 – REVISED APRIL 2013 DS92LV3221/DS92LV3222 20-50 MHz 32-Bit...
Datasheet PDF File DS92LV3222 PDF File

DS92LV3222
DS92LV3222

Overview
DS92LV3221, DS92LV3222 www.
ti.
com SNLS319C – OCTOBER 2009 – REVISED APRIL 2013 DS92LV3221/DS92LV3222 20-50 MHz 32-Bit Channel Link II Serializer / Deserializer Check for Samples: DS92LV3221, DS92LV3222 FEATURES 1 •2 Wide Operating Range Embedded Clock SER/DES – Up to 32-bit Parallel LVCMOS Data – 20 to 50 MHz Parallel Clock – Up to 1.
6 Gbps Application Data Paylod • Simplified Clocking Architecture – No Separate Serial Clock Line – No Reference Clock Required – Receiver Locks to Random Data • On-chip Signal Conditioning for Robust Serial Connectivity – Transmit Pre-Emphasis – Data Randomization – DC-Balance Encoding – Receive Channel Deskew – Supports up to 10m CAT-5 at 1.
6Gbps • Integrated LVDS Terminations • Built-in AT-SPEED BIST for End-To-End System Testing • AC-Coupled Interconnect for Isolation and Fault Protection • > 4KV HBM ESD Protection • Space-Saving 64-pin TQFP Package • Full Industrial Temperature Range: -40° to +85°C APPLICATIONS • Industrial Imaging (Machine-vision) and Control • Security and Surveillance Cameras and Infrastructure • Medical Imaging DESCRIPTION The DS92LV3221 (SER) serializes a 32-bit data bus into 2 embedded clock LVDS serial channels for a data payload rate up to 1.
6 Gbps over cables such as CATx, or backplanes FR-4 traces.
The companion DS92LV3222 (DES) deserializes the 2 LVDS serial data channels, de-skews channel-to-channel delay variations and converts the LVDS data stream back into a 32-bit LVCMOS parallel data bus.
On-chip data Randomization/Scrambling and DC balance encoding and selectable serializer Preemphasis ensure a robust, low-EMI transmission over longer, lossy cables and backplanes.
The Deserializer automatically locks to incoming data without an external reference clock or special sync patterns, providing an easy “plug-and-lock” operation.
By embedding the clock in the data payload and including signal conditioning functions, the ChannelLink II SerDes devices reduce trace count, eliminate skew issues, simplify...


Similar Datasheet


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)