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DS92LV3222

National Semiconductor Corporation
Part Number DS92LV3222
Manufacturer National Semiconductor Corporation
Description (DS92LV3221 / DS92LV3222) 20-50 MHz 32-Bit Channel Link II Serializer/Deserializer
Published Dec 21, 2009
Detailed Description DS92LV3221/DS92LV3222 20-50 MHz 32-Bit Channel Link II Serializer/Deserializer October 21, 2009 DS92LV3221/DS92LV3222 ...
Datasheet PDF File DS92LV3222 PDF File

DS92LV3222
DS92LV3222

Overview
DS92LV3221/DS92LV3222 20-50 MHz 32-Bit Channel Link II Serializer/Deserializer October 21, 2009 DS92LV3221/DS92LV3222 20-50 MHz 32-Bit Channel Link II Serializer/Deserializer General Description The DS92LV3221 (SER) serializes a 32-bit data bus into 2 embedded clock LVDS serial channels for a data payload rate up to 1.
6 Gbps over cables such as CATx, or backplanes FR-4 traces.
The companion DS92LV3222 (DES) deserializes the 2 LVDS serial data channels, de-skews channel-to-channel delay variations and converts the LVDS data stream back into a 32-bit LVCMOS parallel data bus.
On-chip data Randomization/Scrambling and DC balance encoding and selectable serializer Pre-emphasis ensure a robust, low-EMI transmission over longer, lossy cables and backplanes.
The Deserializer automatically locks to incoming data without an external reference clock or special sync patterns, providing an easy “plug-and-lock” operation.
By embedding the clock in the data payload and including signal conditioning functions, the Channel-Link II SerDes devices reduce trace count, eliminate skew issues, simplify design effort and lower cable/connector cost for a wide variety of video, control and imaging applications.
A built-in ATSPEED BIST feature validates link integrity and may be used for system diagnostics.
Features ■ Wide Operating Range Embedded Clock SER/DES — Up to 32-bit parallel LVCMOS data — 20 to 50 MHz parallel clock — Up to 1.
6 Gbps application data paylod Simplified Clocking Architecture — No separate serial clock line — No reference clock required — Receiver locks to random data On-chip Signal Conditioning for Robust Serial Connectivity — Transmit Pre-Emphasis — Data randomization — DC-balance encoding — Receive channel deskew — Supports up to 10m CAT-5 at 1.
6Gbps Integrated LVDS Terminations Built-in AT-SPEED BIST for end-to-end system testing AC-coupled interconnect for isolation and fault protection > 4KV HBM ESD protection Space-saving 64-pin TQFP package Full industrial t...


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