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74ACT843

Fairchild Semiconductor
Part Number 74ACT843
Manufacturer Fairchild Semiconductor
Description 9-Bit Transparent Latch
Published Apr 3, 2005
Detailed Description 74ACT843 9-Bit Transparent Latch July 1988 Revised September 2000 74ACT843 9-Bit Transparent Latch General Description...
Datasheet PDF File 74ACT843 PDF File

74ACT843
74ACT843

Overview
74ACT843 9-Bit Transparent Latch July 1988 Revised September 2000 74ACT843 9-Bit Transparent Latch General Description The ACT843 bus interface latch is designed to eliminate the extra packages required to buffer existing latches and provide extra data width for wider address/data paths.
Features s TTL compatible inputs s 3-STATE outputs for bus interfacing Ordering Code: Order Number 74ACT843SC 74ACT843SPC Package Number M24B N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.
300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.
300 Wide Device also available in Tape and Reel.
Specify by appending suffix letter “X” to the ordering code.
(SPC not available in Tape and Reel.
) Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names D0–D8 O0–O8 OE LE CLR PRE Description Data Inputs Data Outputs Output Enable Latch Enable Clear Preset FACT is a trademark of Fairchild Semiconductor Corporation © 2000 Fairchild Semiconductor Corporation DS009800 www.
fairchildsemi.
com 74ACT843 Functional Description The ACT843 consists of nine D-type latches with 3-STATE outputs.
The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH.
This allows asynchronous operation, as the output transition follows the data in transition.
On the LE HIGH-to-LOW transition, the data that meets the setup times is latched.
Data appears on the bus when the Output Enable (OE) is LOW.
When OE is HIGH, the bus output is in the high impedance state.
In addition to the LE and OE pins, the ACT843 has a Clear (CLR) pin and a Preset (PRE) pin.
These pins are ideal for parity bus interfacing in high performance systems.
When CLR is LOW, the outputs are LOW if OE is LOW.
When CLR is HIGH, data can be entered into the latch.
When PRE is LOW, the outputs are HIGH if OE is LOW.
Preset overrides CLR.
Function Tables Inputs CLR H H H H H H H L L L H H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High...


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