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74ACT899

Fairchild Semiconductor
Part Number 74ACT899
Manufacturer Fairchild Semiconductor
Description 9-Bit Latchable Transceiver
Published Apr 3, 2005
Detailed Description 74ACT899 9-Bit Latchable Transceiver with Parity Generator/Checker January 1990 Revised December 1998 74ACT899 9-Bit L...
Datasheet PDF File 74ACT899 PDF File

74ACT899
74ACT899

Overview
74ACT899 9-Bit Latchable Transceiver with Parity Generator/Checker January 1990 Revised December 1998 74ACT899 9-Bit Latchable Transceiver with Parity Generator/Checker General Description The ACT899 is a 9-bit to 9-bit parity transceiver with transparent latches.
The device can operate as a feed-through transceiver or it can generate/check parity from the 8-bit data busses in either direction.
The ACT899 features independent latch enables for the A-to-B direction and the B-toA direction, a select pin for ODD/EVEN parity, and separate error signal output pins for checking parity.
Features s Latchable transceiver with output sink of 24 mA s Option to select generate parity and check or “feed-through” data/parity in directions A-to-B or B-to-A s Independent latch enable for A-to-B and B-to-A directions s Select pin for ODD/EVEN parity s ERRA and ERRB output pins for parity checking s Ability to simultaneously generate and check parity s May be used in system applications in place of the 280 s May be used in system applications in place of the 657 and 373 (no need to change T/R to check parity) Ordering Code: Order Number 74ACT899QC Package Number V28A Package Description 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.
450” Square Device also available in Tape and Reel.
Specify by appending suffix letter “X” to the ordering code.
Logic Symbol Connection Diagram Pin Assignment for PCC FACT™ is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS010637.
prf www.
fairchildsemi.
com 74ACT899 Pin Descriptions Pin Names A0–A7 B0–B7 APAR, BPAR ODD/EVEN GBA, GAB SEL LEA, LEB ERRA, ERRB Description A Bus Data Inputs/Data Outputs B Bus Data Inputs/Data Outputs A and B Bus Parity Inputs ODD/EVEN Parity Select, Active LOW for EVEN Parity Output Enables for A or B Bus, Active LOW Select Pin for Feed-Through or Generate Mode, LOW for Generate Mode Latch Enables for A and B Latches, HIGH for Transparent Mode Error Signa...


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