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74ALVCH16600

NXP
Part Number 74ALVCH16600
Manufacturer NXP
Description 18-bit universal bus transceiver
Published Apr 3, 2005
Detailed Description INTEGRATED CIRCUITS 74ALVCH16600 18-bit universal bus transceiver (3-State) Product specification Supersedes data of 19...
Datasheet PDF File 74ALVCH16600 PDF File

74ALVCH16600
74ALVCH16600

Overview
INTEGRATED CIRCUITS 74ALVCH16600 18-bit universal bus transceiver (3-State) Product specification Supersedes data of 1998 Aug IC24 Data Handbook 1998 Sep 24 Philips Semiconductors Philips Semiconductors Product specification 18-bit universal bus transceiver (3-State) 74ALVCH16600 FEATURES • Complies with JEDEC standard no.
8-1A.
• CMOS low power consumption • Direct interface with TTL levels • Current drive ± 24 mA at 3.
0 V • All inputs have bus hold circuitry • Output drive capability 50Ω transmission lines @ 85°C • MULTIBYTETM flow-through standard pin-out architecture • Low inductance multiple VCC and ground pins for minimum noise and ground bounce DESCRIPTION The 74ALVCH16600 is an 18-bit universal transceiver featuring non-inverting 3-State bus compatible outputs in both send and receive directions.
Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs.
For A-to-B data flow, the device operates in the transparent mode when LEAB is High.
When LEAB is Low, the A data is latched if CPAB is held at a High or Low logic level.
If LEAB is Low, the A-bus data is stored in the latch/flip-flop on the High-to-Low transition of CPAB.
When OEAB is Low, the outputs are active.
When OEAB is High, the outputs are in the high-impedance state.
The High clock can be controlled with the clock-enable inputs (CEBA/CEAB).
Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA.
To ensure the high impedance state during power up or power down, OEBA and OEAB should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver.
Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr = tf = 2.
5ns SYMBOL tPHL/tPLH CI/O CI CPD PARAMETER Propagation delay An, Bn to Bn, An Input/Output capacita...


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