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74ALVCH16823

NXP
Part Number 74ALVCH16823
Manufacturer NXP
Description 18-bit bus-interface D-type flip-flop
Published Apr 3, 2005
Detailed Description INTEGRATED CIRCUITS 74ALVCH16823 18-bit bus-interface D-type flip-flop with reset and enable (3-State) Product specific...
Datasheet PDF File 74ALVCH16823 PDF File

74ALVCH16823
74ALVCH16823

Overview
INTEGRATED CIRCUITS 74ALVCH16823 18-bit bus-interface D-type flip-flop with reset and enable (3-State) Product specification IC24 Data Handbook 1998 Jul 29 Philips Semiconductors Philips Semiconductors Product specification 18-bit D-type flip-flop (3-State) 74ALVCH16823 FEATURES • Wide supply voltage range of 1.
2V to 3.
6V • Complies with JEDEC standard no.
8-1A.
• CMOS low power consumption • Direct interface with TTL levels • Current drive ± 24 mA at 3.
0 V • Multibyte™flow-through standard pin-out architecture • Low inductance multiple VCC and GND pins to minimize noise and ground bounce DESCRIPTION The 74ALVCH16823 is a 18-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications.
Incorporates bushold data inputs which eliminate the need for external pull-up resistors to hold unused inputs.
The74ALVCH16823 consists of two sections of nine edge-triggered flip-flops.
A clock (CP) input, an output-enable (OE) input, a Master reset (MR) input and a clock-enable( CE) input are provided for each total 9-bit section.
With the clock-enable (CE) input LOW, the D-type flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH CP transition.
Taking CE HIGH disables the clock buffer, thus latching the outputs.
Taking the Master reset (MR) input LOW causes all the Q outputs to go LOW independently of the clock.
When OE is LOW, the contents of the flip-flops are available at the outputs.
When the OE is HIGH, the outputs go to the high impedance OFF-state.
Operation of the OE input does not affect the state of flip-flops.
Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
• All data inputs have bus hold • Output drive capability 50Ω transmission lines @ 85°C QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr = tf ≤ 2.
5ns SYMBOL tPHL/tPLH Fmax CI CPD PARAMETER Propagation delay CP to ...


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