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74ALVCH16827

NXP
Part Number 74ALVCH16827
Manufacturer NXP
Description 20-bit buffer/line driver
Published Apr 3, 2005
Detailed Description INTEGRATED CIRCUITS 74ALVCH16827 20-bit buffer/line driver, non-inverting (3-State) Product specification IC24 Data Han...
Datasheet PDF File 74ALVCH16827 PDF File

74ALVCH16827
74ALVCH16827

Overview
INTEGRATED CIRCUITS 74ALVCH16827 20-bit buffer/line driver, non-inverting (3-State) Product specification IC24 Data Handbook 1998 Jul 27 Philips Semiconductors Philips Semiconductors Product specification 20-bit buffer/line driver, non-inverting (3-State) 74ALVCH16827 FEATURES • Wide supply voltage range of 1.
2V to 3.
6V • Complies with JEDEC standard no.
8-1A • Wide supply voltage range of 1.
2V to 3.
6V • CMOS low power consumption • Direct interface with TTL levels • Universal bus transceiver with D-type latches and D-type flip-flops capable of operating in transparent, latched, clocked or clocked-enabled mode.
DESCRIPTION The 74ALVCH16827 is a 20-bit non-inverting buffer/driver with 3-State outputs for bus oriented applications.
The 74ALVCH16827 consists of two 10-bit sections with separate output enable signals.
For either 10-bit buffer section, the two output enable (1OE1 and 1OE2 or 2OE1 and 2OE2) inputs must both be active.
If either output enable input is high, the outputs of that 10-bit buffer section are in high impedance state.
The 74ALVCH16827 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level.
This feature eliminates the need for external pull-up or pull-down resistors.
• MULTIBYTETM flow-through standard pin-out architecture • Low inductance multiple VCC and GND pins for minimum noise and ground bounce • Current drive ±24 mA at 3.
0 V • All inputs have bus hold circuitry • Output drive capability 50Ω transmission lines @ 85°C • 3-State non-inverting outputs for bus oriented applications QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr = tf = 2.
5ns SYMBOL PARAMETER Propagation delay tPHL/tPLH CP to Qn CI Input capacitance CPD Power dissipation dissi ation capacitance ca acitance per er latch CONDITIONS VCC = 2.
5V, CL = 30pF VCC = 3.
3V, CL = 50pF VI = GND to VCC1 Output enabled Output disabled TYPICAL 2.
0 2.
0 5 20 3 UNIT ns pF pF F NOTES: 1.
CPD is used to determine the dynamic power di...


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